[coreboot-gerrit] Change in coreboot[master]: [UNTESTED]nb/intel/gm45/raminit: Support MTB other than 1/8ns

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19184 )

Change subject: [UNTESTED]nb/intel/gm45/raminit: Support MTB other than 1/8ns
......................................................................

[UNTESTED]nb/intel/gm45/raminit: Support MTB other than 1/8ns

Timings and MTB are computed in units of 1/256ns to achieve this.

Change-Id: Ie8d37fdc45b3bb67e50cf2de2311a44f45a84f69
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/gm45/raminit.c
1 file changed, 16 insertions(+), 17 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/19184/1

diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 0435cdd..a908771 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -266,12 +266,6 @@
 	/* How to check if burst length is 8?
 	   Other values are not supported, are they even possible? */
 
-	if (!test_dimm(sysinfo, dimm, 10, 0xff, 1))
-		die("Code assumes 1/8ns MTB\n");
-
-	if (!test_dimm(sysinfo, dimm, 11, 0xff, 8))
-		die("Code assumes 1/8ns MTB\n");
-
 	if (!test_dimm(sysinfo, dimm, 62, 0x9f, 0) &&
 			!test_dimm(sysinfo, dimm, 62, 0x9f, 1) &&
 			!test_dimm(sysinfo, dimm, 62, 0x9f, 2) &&
@@ -303,6 +297,7 @@
 		unsigned int banks;
 		unsigned int ranks;
 		unsigned int cas_latencies;
+		unsigned int mtb;
 		unsigned int tAAmin;
 		unsigned int tCKmin;
 		unsigned int width;
@@ -317,6 +312,8 @@
 /*
  * This function collects RAM characteristics from SPD, assuming that RAM
  * is generally within chipset's requirements, since verify_ddr3() passed.
+ *
+ * Timings are in units of 1/256 ns.
  */
 static void collect_ddr3(sysinfo_t *const sysinfo, spdinfo_t *const config)
 {
@@ -325,7 +322,7 @@
 	while (mask != 0) {
 		/* FIXME: support several dimms on same channel.  */
 		if ((mask & 1) && sysinfo->spd_map[2 * cur]) {
-			int tmp;
+			int tmp, mtb;
 			const int smb_addr = sysinfo->spd_map[2 * cur];
 
 			config->channel[cur].rows = ((smbus_read_byte(smb_addr, 5) >> 3) & 7) + 12;
@@ -340,18 +337,21 @@
 			config->channel[cur].cas_latencies =
 				((smbus_read_byte(smb_addr, 15) << 8) | smbus_read_byte(smb_addr, 14))
 				<< 4; /* so bit x is CAS x */
-			config->channel[cur].tAAmin = smbus_read_byte(smb_addr, 16); /* in MTB */
-			config->channel[cur].tCKmin = smbus_read_byte(smb_addr, 12); /* in MTB */
+			mtb = (smbus_read_byte(smb_addr, 10) << 8)
+				/ smbus_read_byte(smb_addr, 11); /* MTB in 256th of a ns */
+			config->channel[cur].tAAmin = smbus_read_byte(smb_addr, 16) * mtb;
+			config->channel[cur].tCKmin = smbus_read_byte(smb_addr, 12) * mtb;
 
 			config->channel[cur].width = smbus_read_byte(smb_addr, 7) & 7;
 			config->channel[cur].page_size = config->channel[cur].width *
 								(1 << config->channel[cur].cols); /* in Bytes */
 
 			tmp = smbus_read_byte(smb_addr, 21);
-			config->channel[cur].tRAS = smbus_read_byte(smb_addr, 22) | ((tmp & 0xf) << 8);
-			config->channel[cur].tRP = smbus_read_byte(smb_addr, 20);
-			config->channel[cur].tRCD = smbus_read_byte(smb_addr, 18);
-			config->channel[cur].tWR = smbus_read_byte(smb_addr, 17);
+			config->channel[cur].tRAS = (smbus_read_byte(smb_addr, 22)
+						| ((tmp & 0xf) << 8)) * mtb;
+			config->channel[cur].tRP = smbus_read_byte(smb_addr, 20) * mtb;
+			config->channel[cur].tRCD = smbus_read_byte(smb_addr, 18) * mtb;
+			config->channel[cur].tWR = smbus_read_byte(smb_addr, 17) * mtb;
 
 			config->channel[cur].raw_card = smbus_read_byte(smb_addr, 62) & 0x1f;
 		}
@@ -410,7 +410,6 @@
 	   CAS >= roundup(tAA_min/tCK)
 	   CAS supported
 	   Clock(MHz) = 1000 / tCK(ns)
-	   Clock(MHz) = 8000 / tCK(MTB)
 	   AND BTW: Clock(MT) = 2000 / tCK(ns) - intel uses MTs but calls them MHz
 	 */
 	int i;
@@ -435,7 +434,7 @@
 		case FSB_CLOCK_667MHz:	fsb_mhz =  667; break;
 	}
 
-	unsigned int clock = 8000 / tCKmin;
+	unsigned int clock = 256000 / tCKmin;
 	if ((clock > sysinfo->max_ddr3_mt / 2) || (clock > fsb_mhz / 2)) {
 		int new_clock = min(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2);
 		printk(BIOS_SPEW, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n",
@@ -450,13 +449,13 @@
 	while (1) {
 		if (!clock)
 			die("Couldn't find compatible clock / CAS settings.\n");
-		tCKproposed = 8000 / clock;
+		tCKproposed = 256000 / clock;
 		CAS = ROUNDUP_DIV(tAAmin, tCKproposed);
 		printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", CAS, tCKproposed);
 		for (; CAS <= DDR3_MAX_CAS; ++CAS)
 			if (cas_latencies & (1 << CAS))
 				break;
-		if ((CAS <= DDR3_MAX_CAS) && (CAS * tCKproposed < 160)) {
+		if ((CAS <= DDR3_MAX_CAS) && (CAS * tCKproposed < 5120)) {
 			/* Found good CAS. */
 			printk(BIOS_SPEW, "Found compatible clock / CAS pair: %u / %u.\n", clock, CAS);
 			break;

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie8d37fdc45b3bb67e50cf2de2311a44f45a84f69
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>