[coreboot-gerrit] Change in coreboot[master]: google/kahlee: Enable ChromeEC
Marc Jones (Code Review)
gerrit at coreboot.org
Thu Apr 6 19:10:06 CEST 2017
Marc Jones has uploaded a new change for review. ( https://review.coreboot.org/19166 )
Change subject: google/kahlee: Enable ChromeEC
......................................................................
google/kahlee: Enable ChromeEC
Add the Kconfig options to build ChromeEC, use the ChromeEC switches,
and decode the ChromeEC on LPC.
Change-Id: Iac06b659e5274be2d7c3b34534e05adad3e3eb3d
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/google/kahlee/Kconfig
M src/mainboard/google/kahlee/Makefile.inc
M src/mainboard/google/kahlee/chromeos.c
A src/mainboard/google/kahlee/ec.c
A src/mainboard/google/kahlee/ec.h
M src/mainboard/google/kahlee/mainboard.c
6 files changed, 156 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/19166/1
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index e360c47..9c56396 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -26,7 +26,10 @@
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
+ select DRIVERS_PS2_KEYBOARD
select MAINBOARD_HAS_CHROMEOS
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_LPC
config MAINBOARD_DIR
string
@@ -51,6 +54,8 @@
config CHROMEOS
select VBOOT_MOCK_SECDATA
select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
+ select EC_GOOGLE_CHROMEEC_SWITCHES
+ select VBOOT_LID_SWITCH
config CBFS_SIZE
hex
diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc
index c4b123f..9acbf79 100644
--- a/src/mainboard/google/kahlee/Makefile.inc
+++ b/src/mainboard/google/kahlee/Makefile.inc
@@ -23,3 +23,7 @@
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+romstaqe-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c
index fedde81..3e61d12 100644
--- a/src/mainboard/google/kahlee/chromeos.c
+++ b/src/mainboard/google/kahlee/chromeos.c
@@ -15,12 +15,12 @@
* GNU General Public License for more details.
*/
-#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#include <southbridge/amd/pi/hudson/gpio.h>
-
-#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
+
+#include <console/console.h>
+#include <ec.h>
+#include <cpu/amd/pi/car.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
@@ -33,61 +33,15 @@
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
-#endif /* ENV_RAMSTAGE */
-
-int get_developer_mode_switch(void)
-{
- return 1;
-}
int get_write_protect_state(void)
{
return 0;
}
-int get_lid_switch(void)
+
+
+void car_mainboard_post_console_init(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- /* Read lid switch state from the EC. */
- return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
-
- /* Lid always open */
- return 1;
-}
-
-int get_recovery_mode_switch(void)
-{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
- /* Check for dedicated recovery switch first. */
- if (google_chromeec_get_switches() &
- EC_SWITCH_DEDICATED_RECOVERY)
- return 1;
-
- /* Otherwise check if the EC has posted the keyboard recovery
- * event. */
- return !!(google_chromeec_get_events_b() &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
- }
-
- return 0;
-}
-
-int clear_recovery_mode_switch(void)
-{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- /* Clear keyboard recovery event. */
- return google_chromeec_clear_events_b(
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
-
- return 0;
-}
-
-static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
- CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-};
-
-void mainboard_chromeos_acpi_generate(void)
-{
- chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+ mainboard_ec_init();
}
diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c
new file mode 100644
index 0000000..4cd6923
--- /dev/null
+++ b/src/mainboard/google/kahlee/ec.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <rules.h>
+#include <hudson.h>
+#include <ec.h>
+
+static void ramstage_ec_init(void)
+{
+ printk(BIOS_ERR, "mainboard: EC init\n");
+
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0)
+ ;
+
+ /* Restore SCI event mask */
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ }
+
+ /* Clear wake event mask */
+ google_chromeec_set_wake_mask(0);
+}
+
+static void early_ec_init(void)
+{
+#ifdef __PRE_RAM__
+ uint16_t ec_ioport_base;
+ size_t ec_ioport_size;
+
+ /*
+ * Set up LPC decoding for the ChromeEC I/O port ranges:
+ * - Ports 62/66, 60/64, and 200->208
+ * -- set by hudson_lpc_decode() in pre
+ * - ChromeEC specific communication I/O ports.
+ */
+ google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
+ printk(BIOS_DEBUG,
+ "LPC Setup google_chromeec_ioport_range: %08x, %08x\n",
+ (u32)ec_ioport_base, (u32)ec_ioport_size);
+ lpc_wideio_512_window(ec_ioport_base);
+#endif //_PRE_RAM_
+}
+
+void mainboard_ec_init(void)
+{
+ if (ENV_RAMSTAGE)
+ ramstage_ec_init();
+ else
+ early_ec_init();
+}
diff --git a/src/mainboard/google/kahlee/ec.h b/src/mainboard/google/kahlee/ec.h
new file mode 100644
index 0000000..6340b69
--- /dev/null
+++ b/src/mainboard/google/kahlee/ec.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
+#define EC_SCI_GPI 24
+/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI 23
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+
+#endif
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 632c800..bdb45b8 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -18,6 +18,7 @@
#include <arch/acpi.h>
#include <agesawrapper.h>
#include <southbridge/amd/common/amd_pci_util.h>
+#include <ec.h>
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -86,6 +87,8 @@
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
+
+ mainboard_ec_init();
}
struct chip_operations mainboard_ops = {
--
To view, visit https://review.coreboot.org/19166
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iac06b659e5274be2d7c3b34534e05adad3e3eb3d
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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