[coreboot-gerrit] Change in coreboot[master]: google/kahlee: Add ChromeOS options
Marc Jones (Code Review)
gerrit at coreboot.org
Thu Apr 6 19:10:05 CEST 2017
Marc Jones has uploaded a new change for review. ( https://review.coreboot.org/19164 )
Change subject: google/kahlee: Add ChromeOS options
......................................................................
google/kahlee: Add ChromeOS options
Add the basics for building as a ChromeOS device.
There are some updates required to depthcharge, vboot, GPIOs,
and the Google EC before we have a complete-ish system.
Change-Id: I9e442f5f880813e86dfd4918ecbed3eaa381f6cb
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/google/kahlee/Kconfig
M src/mainboard/google/kahlee/Makefile.inc
A src/mainboard/google/kahlee/chromeos.c
A src/mainboard/google/kahlee/chromeos.fmd
4 files changed, 143 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/19164/1
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 5fae751..0eb026c 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -26,6 +26,7 @@
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
+ select MAINBOARD_HAS_CHROMEOS
config MAINBOARD_DIR
string
@@ -51,4 +52,12 @@
bool
default y
+config CHROMEOS
+ select VBOOT_MOCK_SECDATA
+ select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
+
+config CBFS_SIZE
+ hex
+ default 0x00210000 if CHROMEOS
+
endif # BOARD_GOOGLE_KAHLEE
diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc
index 72cd042..c4b123f 100644
--- a/src/mainboard/google/kahlee/Makefile.inc
+++ b/src/mainboard/google/kahlee/Makefile.inc
@@ -1,7 +1,7 @@
#
# This file is part of the coreboot project.
#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
+# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -19,3 +19,7 @@
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c
new file mode 100644
index 0000000..fedde81
--- /dev/null
+++ b/src/mainboard/google/kahlee/chromeos.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <southbridge/amd/pi/hudson/gpio.h>
+
+#if ENV_RAMSTAGE
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif /* ENV_RAMSTAGE */
+
+int get_developer_mode_switch(void)
+{
+ return 1;
+}
+
+int get_write_protect_state(void)
+{
+ return 0;
+}
+
+int get_lid_switch(void)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ /* Read lid switch state from the EC. */
+ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+
+ /* Lid always open */
+ return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ /* Check for dedicated recovery switch first. */
+ if (google_chromeec_get_switches() &
+ EC_SWITCH_DEDICATED_RECOVERY)
+ return 1;
+
+ /* Otherwise check if the EC has posted the keyboard recovery
+ * event. */
+ return !!(google_chromeec_get_events_b() &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ }
+
+ return 0;
+}
+
+int clear_recovery_mode_switch(void)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ /* Clear keyboard recovery event. */
+ return google_chromeec_clear_events_b(
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+
+ return 0;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/kahlee/chromeos.fmd b/src/mainboard/google/kahlee/chromeos.fmd
new file mode 100644
index 0000000..52aa37e
--- /dev/null
+++ b/src/mainboard/google/kahlee/chromeos.fmd
@@ -0,0 +1,36 @@
+FLASH at 0xff800000 0x800000 {
+SI_ALL at 0x0 0xCB000 {
+ UNUSED at 0x00000 0x20000
+ AMD_FW at 0x20000 0xAB000
+ }
+SI_BIOS at 0xCB000 0x735000 {
+ RW_SECTION_A at 0x0 0x21e000 {
+ VBLOCK_A at 0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x20DFC0
+ RW_FWID_A at 0x21dfc0 0x40
+ }
+ RW_SECTION_B at 0x21e000 0x21e000 {
+ VBLOCK_B at 0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x20DFC0
+ RW_FWID_B at 0x21dfc0 0x40
+ }
+ RW_MRC_CACHE at 0x43C000 0x10000
+ RW_ELOG at 0x44C000 0x4000
+ RW_SHARED at 0x450000 0x4000 {
+ SHARED_DATA at 0x0 0x2000
+ VBLOCK_DEV at 0x2000 0x2000
+ }
+ RW_VPD at 0x454000 0x2000
+ RW_UNUSED at 0x456000 0x4F000
+# RW_LEGACY(CBFS)@0x200000 0x200000
+ WP_RO at 0x4A5000 0x290000 {
+ RO_SECTION at 0x00000 0x290000 {
+ FMAP at 0x0 0x800
+ RO_FRID at 0x800 0x40
+ RO_FRID_PAD at 0x840 0x7c0
+ GBB at 0x1000 0x70000
+ COREBOOT(CBFS)@0x80000 0x210000
+ }
+ }
+ }
+}
--
To view, visit https://review.coreboot.org/19164
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I9e442f5f880813e86dfd4918ecbed3eaa381f6cb
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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