[coreboot-gerrit] Change in coreboot[master]: amd/pi/00670F00: Add AMD PSP support for Stoney Ridge
Marc Jones (Code Review)
gerrit at coreboot.org
Thu Apr 6 19:10:03 CEST 2017
Hello Marshall Dawson,
I'd like you to do a code review. Please visit
https://review.coreboot.org/19157
to review the following change.
Change subject: amd/pi/00670F00: Add AMD PSP support for Stoney Ridge
......................................................................
amd/pi/00670F00: Add AMD PSP support for Stoney Ridge
Add PSP communication support that is not covered by AGESA.
The PSP must be notified DRAM is ready after amdinitpost().
Move amd_intcpuio() to the end of amdinitpost() so that the PSP
decode for notify works.
Change-Id: Icf111470b261d6516b878e88be471967abe681b3
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/cpu/amd/pi/00670F00/romstage.c
M src/northbridge/amd/pi/00670F00/Makefile.inc
A src/northbridge/amd/pi/00670F00/psp.c
A src/northbridge/amd/pi/00670F00/psp.h
M src/northbridge/amd/pi/agesawrapper.c
5 files changed, 210 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19157/1
diff --git a/src/cpu/amd/pi/00670F00/romstage.c b/src/cpu/amd/pi/00670F00/romstage.c
index 6876e17..89be762 100644
--- a/src/cpu/amd/pi/00670F00/romstage.c
+++ b/src/cpu/amd/pi/00670F00/romstage.c
@@ -20,6 +20,7 @@
#include <cpu/amd/pi/car.h>
#include <cpu/amd/pi/00670F00/romstage.h>
#include <console/console.h>
+#include <northbridge/amd/pi/00670F00/psp.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <program_loading.h>
@@ -52,6 +53,8 @@
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+ psp_notify_dram();
+
post_code(0x41);
cbmem_initialize_empty();
diff --git a/src/northbridge/amd/pi/00670F00/Makefile.inc b/src/northbridge/amd/pi/00670F00/Makefile.inc
index cdbcbb2..e4e2781 100644
--- a/src/northbridge/amd/pi/00670F00/Makefile.inc
+++ b/src/northbridge/amd/pi/00670F00/Makefile.inc
@@ -19,3 +19,6 @@
romstage-y += memmap.c
ramstage-y += memmap.c
+
+romstage-y += psp.c
+ramstage-y += psp.c
diff --git a/src/northbridge/amd/pi/00670F00/psp.c b/src/northbridge/amd/pi/00670F00/psp.c
new file mode 100644
index 0000000..769ab25
--- /dev/null
+++ b/src/northbridge/amd/pi/00670F00/psp.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include "Porting.h"
+#include <AMD.h>
+#include <Proc/Psp/PspBaseLib/PspBaseLib.h>
+#include "amdlib.h"
+#include "psp.h"
+
+static const char *psp_status_nobase = "error: PSP BAR3 not assigned";
+static const char *psp_status_halted = "error: PSP in halted state";
+static const char *psp_status_recovery = "error: PSP in recovery mode";
+static const char *psp_status_errcmd = "error: PSP error sending command";
+static const char *psp_status_noerror = "";
+
+static char *status_to_string(pspcmd_status err)
+{
+ switch (err){
+ case pspsts_nobase:
+ return (char *)psp_status_nobase;
+ case pspsts_halted:
+ return (char *)psp_status_halted;
+ case pspsts_recovery:
+ return (char *)psp_status_recovery;
+ case pspsts_send_error:
+ return (char *)psp_status_errcmd;
+ case pspsts_success:
+ default:
+ return (char *)psp_status_noerror;
+ }
+}
+
+static psp_mbox *get_mbox_address(void)
+{
+ UINT32 base; /* UINT32 for compatibility with PspBaseLib */
+ uintptr_t baseptr;
+
+ GetPspBar3Addr(&base);
+
+ if (!base){
+ PspBarInitEarly();
+ GetPspBar3Addr(&base);
+ }
+ baseptr = (uintptr_t)base;
+ return (psp_mbox *)(baseptr + PSP_MAILBOX_BASE);
+}
+
+static pspcmd_status send_psp_command(c2p_mbox_command command, void *buffer)
+{
+ u32 command_reg;
+ pspcmd_status status = pspsts_success;
+
+ psp_mbox *mbox = get_mbox_address();
+ if ((u32)mbox == PSP_MAILBOX_BASE)
+ return pspsts_nobase;
+
+ command_reg = PspLibPciReadPspConfig(PCI_COMMAND);
+ PspLibPciWriteConfig(PCI_COMMAND, command_reg |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ if (mbox->mbox_status & STATUS_HALT){
+ status = pspsts_halted;
+ goto exit;
+ }
+ if (mbox->mbox_status & STATUS_RECOVERY){
+ status = pspsts_recovery;
+ goto exit;
+ }
+
+ while (!(mbox->mbox_status & STATUS_INITIALIZED) || mbox->mbox_command)
+ ; /* wait for initialized and no command in progress */
+
+ mbox->cmd_response = (u64 *)buffer;
+ mbox->mbox_command = command;
+
+ while (mbox->mbox_command)
+ ;
+
+ PspLibPciWriteConfig(PCI_COMMAND, command_reg);
+ if (mbox->mbox_status & STATUS_ERROR ||
+ mbox->mbox_status & STATUS_TERMINATED){
+ status = pspsts_send_error;
+ goto exit;
+ }
+exit:
+ PspLibPciWriteConfig(PCI_COMMAND, command_reg);
+ return status;
+}
+
+/*
+ * Notify the PSP that DRAM is present. Upon receiving this command, the PSP
+ * will load its OS into fenced DRAM that is not accessible to the x86 cores.
+ */
+void psp_notify_dram(void)
+{
+ unaligned_mbox_buffer unaligned;
+ mbox_default_buffer *buffer;
+ pspcmd_status cmd_status;
+
+ buffer = BALIGN32 (&unaligned);
+ printk(BIOS_DEBUG, "PSP: Notify that DRAM is available: ");
+
+ buffer->header.size = sizeof (mbox_default_buffer);
+ buffer->header.status = 0; /* PSP does not report status for this cmd */
+
+ cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, buffer);
+ printk(BIOS_DEBUG, "status=0x%x %s\n", buffer->header.status,
+ status_to_string(cmd_status));
+}
diff --git a/src/northbridge/amd/pi/00670F00/psp.h b/src/northbridge/amd/pi/00670F00/psp.h
new file mode 100644
index 0000000..f9d8950
--- /dev/null
+++ b/src/northbridge/amd/pi/00670F00/psp.h
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AMD_PSP_H
+#define AMD_PSP_H
+
+/* x86 to PSP commands */
+typedef enum {
+ MBOX_BIOS_CMD_DRAM_INFO = 0x01,
+ MBOX_BIOS_CMD_SMM_INFO = 0x02,
+ MBOX_BIOS_CMD_SX_INFO = 0x03,
+ MBOX_BIOS_CMD_RSM_INFO = 0x04,
+ MBOX_BIOS_CMD_PSP_QUERY = 0x05,
+ MBOX_BIOS_CMD_BOOT_DONE = 0x06,
+ MBOX_BIOS_CMD_CLEAR_S3_STS = 0x07,
+ MBOX_BIOS_CMD_C3_DATA_INFO = 0x08,
+ MBOX_BIOS_CMD_NOP = 0x09,
+ MBOX_BIOS_CMD_ABORT = 0xfe
+} c2p_mbox_command;
+
+typedef enum {
+ STATUS_INITIALIZED = 0x1,
+ STATUS_ERROR = 0x2,
+ STATUS_TERMINATED = 0x4,
+ STATUS_HALT = 0x8,
+ STATUS_RECOVERY = 0x10,
+} mbox_status_bits;
+
+typedef struct {
+ volatile u32 mbox_command;
+ volatile u32 mbox_status;
+ u64 *cmd_response; /* value violates BKDG but matches agesa code */
+} psp_mbox;
+
+typedef struct {
+ u32 size;
+ u32 status;
+} mbox_buffer_header;
+
+typedef struct {
+ mbox_buffer_header header;
+} mbox_default_buffer;
+
+typedef union _mbox_buffer {
+ mbox_default_buffer default_buff;
+ u8 reserved[32];
+} mbox_buffer;
+
+typedef struct {
+ mbox_buffer buffer[2];
+} unaligned_mbox_buffer;
+
+#define BALIGN32(p) ((void *) (((u32)(void *)(p) + 32) & ~0x1f))
+
+typedef enum {
+ pspsts_success = 0,
+ pspsts_nobase = -1,
+ pspsts_halted = -2,
+ pspsts_recovery = -3,
+ pspsts_send_error = -4,
+} pspcmd_status;
+
+void psp_notify_dram(void);
+
+#endif /* AMD_PSP_H */
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 102fa96..5efcdce 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -172,6 +172,9 @@
/* Initialize heap space */
EmptyHeap();
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ amd_initcpuio();
+
return status;
}
@@ -245,9 +248,6 @@
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_MID_PARAMS *MidParam;
-
- /* Enable MMIO on AMD CPU Address Map Controller */
- amd_initcpuio ();
LibAmdMemFill (&AmdParamStruct,
0,
--
To view, visit https://review.coreboot.org/19157
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icf111470b261d6516b878e88be471967abe681b3
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
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