[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add support for GSPI controller

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19099 )

Change subject: soc/intel/skylake: Add support for GSPI controller
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Patch Set 10:

(1 comment)

https://review.coreboot.org/#/c/19099/10/src/soc/intel/skylake/include/soc/iomap.h
File src/soc/intel/skylake/include/soc/iomap.h:

Line 37: #define SKYLAKE_GSPI1_BUS	1
> Why would the mainboard need those values? DRIVER_TPM_SPI_BUS is provided i
Yeah, I was planning on using that in devicetree.cb, something like this:
+       register "gspi[SKYLAKE_GSPI0_BUS]" = "{
+                .speed_mhz = 1,
+                .early_init = 1,
+       }"


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Gerrit-MessageType: comment
Gerrit-Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Gerrit-PatchSet: 10
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-HasComments: Yes