[coreboot-gerrit] Change in coreboot[master]: [WIP]nb/x4x/raminit: Rewrite SPD decode and timing selection

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

    https://review.coreboot.org/19143

to look at the new patch set (#2).

Change subject: [WIP]nb/x4x/raminit: Rewrite SPD decode and timing selection
......................................................................

[WIP]nb/x4x/raminit: Rewrite SPD decode and timing selection

This is mostly written from scratch.

This improves the following:
* This fixes incorrect CAS/Freq detection on DDR2;

* Timing selection does not use loops;

* Removes ddr3 spd decode, since there is no DDR3 raminit. For this it
  would be nice to use similar common functions for DDR3;

* Raminit would bail out if dimm was unsupported, no in some cases it
  just marks the dimm slot as empty;

* It dramatically reduces stack usage since it does not allocate 4
  times 256 bytes to store full SPDs, amongs other unused things that
  were stored in sysinfo.

Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr2.c
M src/northbridge/intel/x4x/x4x.h
3 files changed, 234 insertions(+), 383 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19143/2
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins)