[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add support for GSPI controller
Furquan Shaikh (Code Review)
gerrit at coreboot.org
Wed Apr 5 19:09:38 CEST 2017
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19099 )
Change subject: soc/intel/skylake: Add support for GSPI controller
......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/#/c/19099/10/src/soc/intel/skylake/include/soc/iomap.h
File src/soc/intel/skylake/include/soc/iomap.h:
Line 37: #define SKYLAKE_GSPI1_BUS 1
> These 2 macros aren't used?
Yeah, I had added those for the mainboard to use. But since GSPI0 corresponds to 0 and GSPI1 to 1, I think we can do without these macros as well.
Line 59: #define SPI_BASE_ADDRESS 0xfe010000
> Maybe move EARLY_GSPI_BASE_ADDRESS here to form some sort of ordering?
Done
--
To view, visit https://review.coreboot.org/19099
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: comment
Gerrit-Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Gerrit-PatchSet: 10
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-HasComments: Yes
More information about the coreboot-gerrit
mailing list