[coreboot-gerrit] Change in coreboot[master]: mainboard/google/poppy: Change SD card detect to GPP_E15

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19107 )

Change subject: mainboard/google/poppy: Change SD card detect to GPP_E15
......................................................................


mainboard/google/poppy: Change SD card detect to GPP_E15

SD card detect pin is moved to GPP_E15 in the next build. Update
device tree and gpio config accordingly.

BUG=b:36012095

Change-Id: Ic0ff72cdcb0f1ca27abc7eb8da9ccd8a21b28522
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
Reviewed-on: https://review.coreboot.org/19107
Tested-by: build bot (Jenkins)
Reviewed-by: Naresh Solanki <naresh.solanki at intel.com>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati at intel.corp-partner.google.com>
---
M src/mainboard/google/poppy/devicetree.cb
M src/mainboard/google/poppy/gpio.h
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Naresh Solanki: Looks good to me, approved
  Aaron Durbin: Looks good to me, approved
  build bot (Jenkins): Verified
  Pratikkumar Prajapati: Looks good to me, but someone else must approve



diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb
index 7bf28d0..fcf1066 100644
--- a/src/mainboard/google/poppy/devicetree.cb
+++ b/src/mainboard/google/poppy/devicetree.cb
@@ -177,7 +177,7 @@
 	register "tcc_offset" = "10"     # TCC of 90C
 
 	# Use default SD card detect GPIO configuration
-	register "sdcard_cd_gpio_default" = "GPP_A7"
+	register "sdcard_cd_gpio_default" = "GPP_E15"
 
 	device cpu_cluster 0 on
 		device lapic 0 on end
diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h
index 5fa8244..be7a488 100644
--- a/src/mainboard/google/poppy/gpio.h
+++ b/src/mainboard/google/poppy/gpio.h
@@ -48,7 +48,7 @@
 /* ESPI_IO3 */
 /* ESPI_CS# */
 /* SERIRQ */		PAD_CFG_NC(GPP_A6), /* TP44 */
-/* PIRQA# */		PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* SD_CD# */
+/* PIRQA# */		PAD_CFG_NC(GPP_A7),
 /* CLKRUN# */		PAD_CFG_NC(GPP_A8), /* TP45 */
 /* ESPI_CLK */
 /* CLKOUT_LPC1 */	PAD_CFG_NC(GPP_A10),
@@ -166,7 +166,7 @@
 					NF1), /* USB_C0_DP_HPD */
 /* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP,
 					NF1), /* USB_C1_DP_HPD */
-/* DDPD_HPD2 */		PAD_CFG_NC(GPP_E15), /* TP48 */
+/* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP), /* SD_CD# */
 /* DDPE_HPD3 */		PAD_CFG_NC(GPP_E16), /* TP244 */
 /* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 /* DDPB_CTRLCLK */	PAD_CFG_NC(GPP_E18),

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ic0ff72cdcb0f1ca27abc7eb8da9ccd8a21b28522
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati at intel.corp-partner.google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: build bot (Jenkins)