[coreboot-gerrit] Change in coreboot[master]: soc/intel & sb/intel/*/acpi/*.asl: Change Device(TIMR) to De...
HAOUAS Elyes (Code Review)
gerrit at coreboot.org
Wed Apr 5 11:45:04 CEST 2017
HAOUAS Elyes has uploaded a new change for review. ( https://review.coreboot.org/19138 )
Change subject: soc/intel & sb/intel/*/acpi/*.asl: Change Device(TIMR) to Device(TMR)
......................................................................
soc/intel & sb/intel/*/acpi/*.asl: Change Device(TIMR) to Device(TMR)
Change-Id: I1435d55b35c022ea09a8a2c36257eb06d1ef72ed
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/soc/intel/baytrail/acpi/lpc.asl
M src/soc/intel/braswell/acpi/lpc.asl
M src/soc/intel/broadwell/acpi/lpc.asl
M src/soc/intel/fsp_baytrail/acpi/lpc.asl
M src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
M src/soc/intel/sch/acpi/lpc.asl
M src/soc/intel/skylake/acpi/lpc.asl
M src/southbridge/intel/bd82x6x/acpi/lpc.asl
M src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl
M src/southbridge/intel/fsp_i89xx/acpi/lpc.asl
M src/southbridge/intel/fsp_rangeley/acpi/lpc.asl
M src/southbridge/intel/i82801gx/acpi/lpc.asl
M src/southbridge/intel/i82801ix/acpi/lpc.asl
M src/southbridge/intel/lynxpoint/acpi/lpc.asl
14 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/19138/1
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index 9512032..7565b90 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -122,7 +122,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index bf0ba4b..02c6df6 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -124,7 +124,7 @@
})
}
- Device (TIMR) /* Intel 8254 timer */
+ Device (TMR) /* Intel 8254 timer */
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl
index 70dd6e5..f186353 100644
--- a/src/soc/intel/broadwell/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/acpi/lpc.asl
@@ -187,7 +187,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name (_HID, EISAID("PNP0100"))
Name (_CRS, ResourceTemplate() {
diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
index 9512032..7565b90 100644
--- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
@@ -122,7 +122,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
index 6a7a2f1..72182f6 100644
--- a/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
+++ b/src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
@@ -79,7 +79,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/soc/intel/sch/acpi/lpc.asl b/src/soc/intel/sch/acpi/lpc.asl
index 518bdae..a89b2cb 100644
--- a/src/soc/intel/sch/acpi/lpc.asl
+++ b/src/soc/intel/sch/acpi/lpc.asl
@@ -188,7 +188,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/soc/intel/skylake/acpi/lpc.asl b/src/soc/intel/skylake/acpi/lpc.asl
index 5263486..9b89b54 100644
--- a/src/soc/intel/skylake/acpi/lpc.asl
+++ b/src/soc/intel/skylake/acpi/lpc.asl
@@ -127,7 +127,7 @@
})
}
- Device (TIMR)
+ Device (TMR)
{
Name (_HID, EISAID ("PNP0100"))
Name (_DDN, "8254 Timer")
diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl
index 5204b29..f7b7b18 100644
--- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl
@@ -204,7 +204,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl
index 5204b29..f7b7b18 100644
--- a/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl
+++ b/src/southbridge/intel/fsp_bd82x6x/acpi/lpc.asl
@@ -204,7 +204,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/southbridge/intel/fsp_i89xx/acpi/lpc.asl b/src/southbridge/intel/fsp_i89xx/acpi/lpc.asl
index 5204b29..f7b7b18 100644
--- a/src/southbridge/intel/fsp_i89xx/acpi/lpc.asl
+++ b/src/southbridge/intel/fsp_i89xx/acpi/lpc.asl
@@ -204,7 +204,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl
index b53e98f..447b46a 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl
+++ b/src/southbridge/intel/fsp_rangeley/acpi/lpc.asl
@@ -210,7 +210,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl
index c34602c..564cd8a 100644
--- a/src/southbridge/intel/i82801gx/acpi/lpc.asl
+++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl
@@ -186,7 +186,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl
index 9d27b0b..ebd1306 100644
--- a/src/southbridge/intel/i82801ix/acpi/lpc.asl
+++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl
@@ -186,7 +186,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index aa83981..7f5d1a1 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -211,7 +211,7 @@
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I1435d55b35c022ea09a8a2c36257eb06d1ef72ed
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: HAOUAS Elyes <ehaouas at noos.fr>
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