[coreboot-gerrit] Change in coreboot[master]: soc/intel/lpss: Provide common LPSS clock config

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19115 )

Change subject: soc/intel/lpss: Provide common LPSS clock config
......................................................................

soc/intel/lpss: Provide common LPSS clock config

Since there are multiple controllers in the LPSS and all use the same
frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ.

BUG=b:35583330

Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/common/Kconfig
M src/soc/intel/common/lpss_i2c.c
M src/soc/intel/skylake/Kconfig
4 files changed, 13 insertions(+), 15 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/19115/1

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index ca8f5d0..70d2099 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -117,8 +117,7 @@
 	int
 	default 36
 
-config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
-	depends on SOC_INTEL_COMMON_LPSS_I2C
+config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
 	int
 	default 133
 
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 3d2ced9..919cb50 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -67,20 +67,19 @@
 	help
 	  Provide a mechanism for serial console based ACPI debug.
 
+config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+	int
+	help
+	  The clock speed that the controllers in LPSS(GSPI, I2C) are running
+	  at, in MHz. No default is set here as this is an SOC-specific value
+	  and must be provided by the SOC.
+
 config SOC_INTEL_COMMON_LPSS_I2C
 	bool
 	default n
 	help
 	  This driver supports the Intel Low Power Subsystem (LPSS) I2C
 	  controllers that are based on Synopsys DesignWare IP.
-
-config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
-	int
-	depends on SOC_INTEL_COMMON_LPSS_I2C
-	help
-	  The clock speed that the I2C controller is running at, in MHz.
-	  No default is set here as this is an SOC-specific value and must
-	  be provided by the SOC when it selects this driver.
 
 config SOC_INTEL_COMMON_LPSS_I2C_DEBUG
 	bool "Enable debug output for LPSS I2C transactions"
diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c
index 8dfa3af..851ffb9 100644
--- a/src/soc/intel/common/lpss_i2c.c
+++ b/src/soc/intel/common/lpss_i2c.c
@@ -604,7 +604,7 @@
 					const struct lpss_i2c_bus_config *bcfg,
 					struct lpss_i2c_speed_config *config)
 {
-	const int ic_clk = CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ;
+	const int ic_clk = CONFIG_SOC_INTEL_COMMON_LPSS_CLOCK_MHZ;
 	uint16_t hcnt_min, lcnt_min;
 	int i;
 
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 8ac7263..df8ae2b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -109,10 +109,6 @@
 	int
 	default 36
 
-config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
-	int
-	default 120
-
 config DCACHE_RAM_BASE
 	hex "Base address of cache-as-RAM"
 	default 0xfef00000
@@ -300,4 +296,8 @@
 	help
 	  Choose this option if you want to disable 8042 Keyboard
 
+config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+	int
+	default 120
+
 endif

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>