[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add support for common GSPI controller

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19098 )

Change subject: soc/intel/common: Add support for common GSPI controller
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Patch Set 1:

(4 comments)

https://review.coreboot.org/#/c/19098/1//COMMIT_MSG
Commit Message:

PS1, Line 10: PXA2xx SPI
> What datasheet are you using for the register definitions?
Skylake PCH SPI Host controller programming.


https://review.coreboot.org/#/c/19098/1/src/soc/intel/common/block/gspi/Kconfig
File src/soc/intel/common/block/gspi/Kconfig:

Line 10: 	  The clock speed that the GSPI controller is running at, in MHz.
> Can't we use the lpss Kconfig value for this? Initially assume they are one
Sounds good. I will update that.


https://review.coreboot.org/#/c/19098/1/src/soc/intel/common/block/include/intelblocks/gspi.h
File src/soc/intel/common/block/include/intelblocks/gspi.h:

Line 29: uintptr_t gspi_get_bus_base_address(unsigned int bus);
> For the soc callbacks we should probably put 'soc' in the name so its clear
Okay. I will add that.


Line 41: /* SoC-provided callback for getting desired clock frequency of SPI bus. */
> Are these 'bus' values global in the spi bus namespace? Or relative to the 
These are global in the spi bus namespace. SoCs would be providing a bus# to pci_dev function to identify the SPI controller (GSPI/Fast SPI).


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Gerrit-MessageType: comment
Gerrit-Change-Id: I0eb91eba2c523be457fee8922c44fb500a9fa140
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
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