[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block:[WIP] Add GPIO common code

Hannah Williams (Code Review) gerrit at coreboot.org
Tue Apr 4 03:05:18 CEST 2017


Hannah Williams has posted comments on this change. ( https://review.coreboot.org/18917 )

Change subject: soc/intel/common/block:[WIP] Add GPIO common code
......................................................................


Patch Set 7:

(6 comments)

https://review.coreboot.org/#/c/18917/4/src/soc/intel/common/block/gpio/gpio.c
File src/soc/intel/common/block/gpio/gpio.c:

PS4, Line 50: 
> single DWx register?
will fix - I haven't tested this code yet


https://review.coreboot.org/#/c/18917/7/src/soc/intel/common/block/include/intelblocks/gpio.h
File src/soc/intel/common/block/include/intelblocks/gpio.h:

Line 63: 	GPIO_TX_STATE_MASK = HI,
> Making all these enum means its really hard to share values with ACPI code.
Yes that is why I had to define following at end of this file outside #ifndef __ACPI__
#define PAD_CFG0_TX_STATE		(1 << 0)
#define PAD_CFG0_RX_STATE		(1 << 1)


PS7, Line 73: GPIO
> GPIO means native? native function? This doesn't make sense.
In APL and GLK, there are bits [21:20] which are tx and rx buffer enable for Native (pad mode is non zero) and bits [9:8] is for gpio(pad mode==0).
So for Skylake, what I need to get clarification on is whether these bits are applicable to only pad mode==0 case or for other pad modes too


Line 86: #define M(mode)			(mode)
> This construction is still really odd.
maybe I should change it to 
#define M(mode) (mode & MODE_MASK) where MODE_MASK will be SOC specific. Pad Mode in SKL is bits [11:10] and in APL it is bits [12:10]


Line 86: #define M(mode)			(mode)
> This construction is still really odd.
maybe I should change it to 
#define M(mode) (mode & MODE_MASK) where MODE_MASK will be SOC specific. Pad Mode in SKL is bits [11:10] and in APL it is bits [12:10]


Line 206: 	P_1K2K_H	= 13,     ///< Pull Up  1K
> Why did all these macro names change? Even better would be understanding wh
I'll change to what we had before.


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Gerrit-MessageType: comment
Gerrit-Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Dhaval Sharma <dhaval.v.sharma at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-HasComments: Yes



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