[coreboot-gerrit] Change in coreboot[master]: mainboard/lenovo/t410: turned into a variant of x201
Ani Chang (Code Review)
gerrit at coreboot.org
Tue Apr 4 02:53:15 CEST 2017
Ani Chang has uploaded a new change for review. ( https://review.coreboot.org/19106 )
Change subject: mainboard/lenovo/t410: turned into a variant of x201
......................................................................
mainboard/lenovo/t410: turned into a variant of x201
Is the custom gpio.h used automagically?
Change-Id: I98f774b882817898815ad039efeba1d71ee98ec3
Signed-off-by: Ani Chang <anichang at protonmail.ch>
---
M src/mainboard/lenovo/t410/Kconfig
M src/mainboard/lenovo/t410/Kconfig.name
D src/mainboard/lenovo/t410/Makefile.inc
D src/mainboard/lenovo/t410/acpi/dock.asl
D src/mainboard/lenovo/t410/acpi/ec.asl
D src/mainboard/lenovo/t410/acpi/gpe.asl
D src/mainboard/lenovo/t410/acpi/platform.asl
D src/mainboard/lenovo/t410/acpi/superio.asl
D src/mainboard/lenovo/t410/acpi_tables.c
M src/mainboard/lenovo/t410/board_info.txt
D src/mainboard/lenovo/t410/cmos.default
D src/mainboard/lenovo/t410/cmos.layout
D src/mainboard/lenovo/t410/devicetree.cb
D src/mainboard/lenovo/t410/dock.c
D src/mainboard/lenovo/t410/dock.h
D src/mainboard/lenovo/t410/dsdt.asl
D src/mainboard/lenovo/t410/hda_verb.c
D src/mainboard/lenovo/t410/mainboard.c
D src/mainboard/lenovo/t410/romstage.c
D src/mainboard/lenovo/t410/smi.h
D src/mainboard/lenovo/t410/smihandler.c
21 files changed, 3 insertions(+), 1,586 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/19106/1
diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig
index cf8a8d8..ba6ed13 100644
--- a/src/mainboard/lenovo/t410/Kconfig
+++ b/src/mainboard/lenovo/t410/Kconfig
@@ -1,51 +1,7 @@
if BOARD_LENOVO_T410
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select SYSTEM_TYPE_LAPTOP
- select NORTHBRIDGE_INTEL_NEHALEM
- select SOUTHBRIDGE_INTEL_IBEXPEAK
- select EC_LENOVO_PMH7
- select EC_LENOVO_H8
- select NO_UART_ON_SUPERIO
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select BOARD_ROMSIZE_KB_8192
- select HAVE_ACPI_TABLES
- select INTEL_INT15
- select HAVE_ACPI_RESUME
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
- select SUPERIO_NSC_PC87382
- select DRIVERS_LENOVO_WACOM
- select MAINBOARD_HAS_LPC_TPM
-
-config MAINBOARD_DIR
- string
- default lenovo/t410
-
config MAINBOARD_PART_NUMBER
string
default "ThinkPad T410"
-
-config MMCONF_BASE_ADDRESS
- hex
- default 0xe0000000
-
-config USBDEBUG_HCD_INDEX
- int
- default 2
-
-config DRAM_RESET_GATE_GPIO
- int
- default 10
-
-config MAX_CPUS
- int
- default 4
-
-config CPU_ADDR_BITS
- int
- default 36
endif
diff --git a/src/mainboard/lenovo/t410/Kconfig.name b/src/mainboard/lenovo/t410/Kconfig.name
index 9ef0c7d..d79cf39 100644
--- a/src/mainboard/lenovo/t410/Kconfig.name
+++ b/src/mainboard/lenovo/t410/Kconfig.name
@@ -1,2 +1,2 @@
config BOARD_LENOVO_T410
- bool "ThinkPad T410 (cloned X201 / X201s / X201t)"
+ bool "ThinkPad T410"
diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc
deleted file mode 100644
index 46f98fa..0000000
--- a/src/mainboard/lenovo/t410/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += dock.c
-ramstage-y += dock.c
diff --git a/src/mainboard/lenovo/t410/acpi/dock.asl b/src/mainboard/lenovo/t410/acpi/dock.asl
deleted file mode 100644
index db3e9fe..0000000
--- a/src/mainboard/lenovo/t410/acpi/dock.asl
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "smi.h"
-
-Scope (\_SB)
-{
- Device(DOCK)
- {
- Name(_HID, "ACPI0003")
- Name(_UID, 0x00)
- Name(_PCL, Package() { \_SB } )
-
- Method(_DCK, 1, NotSerialized)
- {
- if (Arg0) {
- /* connect dock */
- Store (1, \GP28)
- Store (1, \_SB.PCI0.LPCB.EC.DKR1)
- Store (1, \_SB.PCI0.LPCB.EC.DKR2)
- Store (1, \_SB.PCI0.LPCB.EC.DKR3)
- } else {
- /* disconnect dock */
- Store (0, \GP28)
- Store (0, \_SB.PCI0.LPCB.EC.DKR1)
- Store (0, \_SB.PCI0.LPCB.EC.DKR2)
- Store (0, \_SB.PCI0.LPCB.EC.DKR3)
- }
- Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0)
- Return (Local0)
- }
-
- Method(_STA, 0, NotSerialized)
- {
- Return (\_SB.PCI0.LPCB.EC.DKR1)
- }
- }
-}
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
- Method(_Q18, 0, NotSerialized)
- {
- Notify(\_SB.DOCK, 3)
- }
-
- Method(_Q45, 0, NotSerialized)
- {
- Notify(\_SB.DOCK, 3)
- }
-
- Method(_Q58, 0, NotSerialized)
- {
- Notify(\_SB.DOCK, 0)
- }
-
- Method(_Q37, 0, NotSerialized)
- {
- Notify(\_SB.DOCK, 0)
- }
-}
diff --git a/src/mainboard/lenovo/t410/acpi/ec.asl b/src/mainboard/lenovo/t410/acpi/ec.asl
deleted file mode 100644
index d631f12..0000000
--- a/src/mainboard/lenovo/t410/acpi/ec.asl
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <ec/lenovo/h8/acpi/ec.asl>
-
-Scope(\_SB.PCI0.LPCB.EC)
-{
-}
diff --git a/src/mainboard/lenovo/t410/acpi/gpe.asl b/src/mainboard/lenovo/t410/acpi/gpe.asl
deleted file mode 100644
index 3cc25b2..0000000
--- a/src/mainboard/lenovo/t410/acpi/gpe.asl
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "smi.h"
-Scope (\_GPE)
-{
- Method(_L18, 0, NotSerialized)
- {
- /* Read EC register to clear wake status */
- Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
- /* So that we don't get a warning that Local0 is unused. */
- Increment (Local0)
- }
-}
diff --git a/src/mainboard/lenovo/t410/acpi/platform.asl b/src/mainboard/lenovo/t410/acpi/platform.asl
deleted file mode 100644
index 3aa12e9..0000000
--- a/src/mainboard/lenovo/t410/acpi/platform.asl
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* These come from the dynamically created CPU SSDT */
-External(PDC0)
-External(PDC1)
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
- APMC, 8, /* APM command */
- APMS, 8 /* APM status */
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
- Store (Arg0, SMIF) /* SMI Function */
- Store (0, TRP0) /* Generate trap */
- Return (SMIF) /* Return value of SMI handler */
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
- /* Remember the OS' IRQ routing choice. */
- Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
- \_SB.PCI0.LPCB.EC.MUTE(1)
- \_SB.PCI0.LPCB.EC.USBP(0)
- \_SB.PCI0.LPCB.EC.RADI(0)
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
- /* Not implemented. */
- Return(Package(){0,0})
-}
-
-/* System Bus */
-
-Scope(\_SB)
-{
- /* This method is placed on the top level, so we can make sure it's the
- * first executed _INI method.
- */
- Method(_INI, 0)
- {
- /* The DTS data in NVS is probably not up to date.
- * Update temperature values and make sure AP thermal
- * interrupts can happen
- */
-
- /* TRAP(71) */ /* TODO */
-
- /* Determine the Operating System and save the value in OSYS.
- * We have to do this in order to be able to work around
- * certain windows bugs.
- *
- * OSYS value | Operating System
- * -----------+------------------
- * 2000 | Windows 2000
- * 2001 | Windows XP(+SP1)
- * 2002 | Windows XP SP2
- * 2006 | Windows Vista
- * ???? | Windows 7
- */
-
- /* Let's assume we're running at least Windows 2000 */
- Store (2000, OSYS)
-
- If (CondRefOf(_OSI)) {
- If (_OSI("Windows 2001")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2001 SP1")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2001 SP2")) {
- Store (2002, OSYS)
- }
-
- If (_OSI("Windows 2001.1")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2001.1 SP1")) {
- Store (2001, OSYS)
- }
-
- If (_OSI("Windows 2006")) {
- Store (2006, OSYS)
- }
-
- If (_OSI("Windows 2006.1")) {
- Store (2006, OSYS)
- }
-
- If (_OSI("Windows 2006 SP1")) {
- Store (2006, OSYS)
- }
-
- If (_OSI("Windows 2009")) {
- Store (2009, OSYS)
- }
-
- If (_OSI("Windows 2012")) {
- Store (2012, OSYS)
- }
- }
- }
-}
diff --git a/src/mainboard/lenovo/t410/acpi/superio.asl b/src/mainboard/lenovo/t410/acpi/superio.asl
deleted file mode 100644
index f2b35ba..0000000
--- a/src/mainboard/lenovo/t410/acpi/superio.asl
+++ /dev/null
@@ -1 +0,0 @@
-#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c
deleted file mode 100644
index 70719e8..0000000
--- a/src/mainboard/lenovo/t410/acpi_tables.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/intel/ibexpeak/nvs.h"
-
-void acpi_create_gnvs(global_nvs_t * gnvs)
-{
-}
diff --git a/src/mainboard/lenovo/t410/board_info.txt b/src/mainboard/lenovo/t410/board_info.txt
index b33cbaf..1f33917 100644
--- a/src/mainboard/lenovo/t410/board_info.txt
+++ b/src/mainboard/lenovo/t410/board_info.txt
@@ -2,5 +2,5 @@
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
-Flashrom support: n
-Release year: 2010
+Flashrom support: y
+Clone of: lenovo/x201
diff --git a/src/mainboard/lenovo/t410/cmos.default b/src/mainboard/lenovo/t410/cmos.default
deleted file mode 100644
index 9f1e31d..0000000
--- a/src/mainboard/lenovo/t410/cmos.default
+++ /dev/null
@@ -1,18 +0,0 @@
-boot_option=Fallback
-baud_rate=115200
-debug_level=Spew
-power_on_after_fail=Disable
-nmi=Enable
-volume=0x3
-first_battery=Primary
-bluetooth=Enable
-wwan=Enable
-wlan=Enable
-touchpad=Enable
-trackpoint=Enable
-fn_ctrl_swap=Disable
-sticky_fn=Disable
-power_management_beeps=Enable
-low_battery_beep=Enable
-sata_mode=AHCI
-usb_always_on=Disable
diff --git a/src/mainboard/lenovo/t410/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout
deleted file mode 100644
index 7270232..0000000
--- a/src/mainboard/lenovo/t410/cmos.layout
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-## Copyright (C) 2013 Vladimir Serbinenko
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96 4 r 0 status_c_rsvd
-#100 1 r 0 uf_flag
-#101 1 r 0 af_flag
-#102 1 r 0 pf_flag
-#103 1 r 0 irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104 7 r 0 status_d_rsvd
-#111 1 r 0 valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112 8 r 0 diag_rsvd1
-
-# -----------------------------------------------------------------
-0 120 r 0 reserved_memory
-#120 264 r 0 unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#390 2 r 0 unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392 3 e 5 baud_rate
-395 4 e 6 debug_level
-#399 1 r 0 unused
-
-#400 8 r 0 reserved for century byte
-
-# coreboot config options: southbridge
-408 1 e 1 nmi
-409 2 e 7 power_on_after_fail
-
-# coreboot config options: EC
-411 1 e 8 first_battery
-412 1 e 1 bluetooth
-413 1 e 1 wwan
-414 1 e 1 touchpad
-415 1 e 1 wlan
-416 1 e 1 trackpoint
-417 1 e 1 fn_ctrl_swap
-418 1 e 1 sticky_fn
-419 1 e 1 power_management_beeps
-420 1 e 1 low_battery_beep
-421 1 e 9 sata_mode
-422 1 e 11 usb_always_on
-#423 1 r 1 unused
-
-# coreboot config options: northbridge
-424 3 e 10 gfx_uma_size
-#427 5 r 0 unused
-432 8 h 0 volume
-
-# coreboot config options: check sums
-984 16 h 0 check_sum
-#1000 24 r 0 amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 1 Emergency
-6 2 Alert
-6 3 Critical
-6 4 Error
-6 5 Warning
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Disable
-7 1 Enable
-7 2 Keep
-8 0 Secondary
-8 1 Primary
-9 0 AHCI
-9 1 Compatible
-10 0 32M
-10 1 48M
-10 2 64M
-10 3 128M
-10 5 96M
-10 6 160M
-11 0 Disable
-11 1 AC and battery
-
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb
deleted file mode 100644
index bd6490e..0000000
--- a/src/mainboard/lenovo/t410/devicetree.cb
+++ /dev/null
@@ -1,178 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/intel/nehalem
- # IGD Displays
- register "gfx.ndid" = "3"
- register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
-
-
- # Enable DisplayPort Hotplug with 6ms pulse
- register "gpu_dp_d_hotplug" = "0x06"
-
- # Enable Panel as LVDS and configure power delays
- register "gpu_panel_port_select" = "0" # LVDS
- register "gpu_panel_power_cycle_delay" = "3"
- register "gpu_panel_power_up_delay" = "250"
- register "gpu_panel_power_down_delay" = "250"
- register "gpu_panel_power_backlight_on_delay" = "2500"
- register "gpu_panel_power_backlight_off_delay" = "2500"
- register "gpu_cpu_backlight" = "0x58d"
- register "gpu_pch_backlight" = "0x061a061a"
- register "gfx.use_spread_spectrum_clock" = "1"
- register "gfx.link_frequency_270_mhz" = "1"
-
- chip ec/lenovo/pmh7
- device pnp ff.1 on # dummy
- end
- register "backlight_enable" = "0x01"
- register "dock_event_enable" = "0x01"
- end
-
- chip ec/lenovo/h8
- device pnp ff.2 on # dummy
- io 0x60 = 0x62
- io 0x62 = 0x66
- io 0x64 = 0x1600
- io 0x66 = 0x1604
- end
-
- register "config0" = "0xa6"
- register "config1" = "0x05"
- register "config2" = "0xa0"
- register "config3" = "0x01"
-
- register "beepmask0" = "0xfe"
- register "beepmask1" = "0x96"
- register "has_power_management_beeps" = "1"
-
- register "event2_enable" = "0xff"
- register "event3_enable" = "0xff"
- register "event4_enable" = "0xf4"
- register "event5_enable" = "0x3c"
- register "event6_enable" = "0x80"
- register "event7_enable" = "0x01"
- register "event8_enable" = "0x01"
- register "event9_enable" = "0xff"
- register "eventa_enable" = "0xff"
- register "eventb_enable" = "0xff"
- register "eventc_enable" = "0xff"
- register "eventd_enable" = "0xff"
- end
-
- device cpu_cluster 0 on
- chip cpu/intel/model_2065x
- device lapic 0 on end
- end
- end
-
- register "pci_mmio_size" = "1024"
-
- device domain 0 on
- device pci 00.0 on # Host bridge
- subsystemid 0x17aa 0x2193
- end
- device pci 02.0 on # VGA controller
- subsystemid 0x17aa 0x215a
- end
- chip southbridge/intel/ibexpeak
- # GPI routing
- # 0 No effect (default)
- # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
- # 2 SCI (if corresponding GPIO_EN bit is also set)
- register "gpi1_routing" = "2"
- register "gpi13_routing" = "2"
-
- register "sata_port_map" = "0x03"
-
- register "gpe0_en" = "0x20022046"
- register "alt_gp_smi_en" = "0x0000"
- register "gen1_dec" = "0x7c1601"
- register "gen2_dec" = "0x0c15e1"
- register "gen3_dec" = "0x1c1681"
- register "gen4_dec" = "0x040069"
-
- register "p_cnt_throttling_supported" = "1"
- register "c2_latency" = "1"
- register "docking_supported" = "1"
-
- register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
-
- device pci 16.2 on # IDE/SATA
- subsystemid 0x17aa 0x2161
- end
-
- device pci 19.0 on # Ethernet
- subsystemid 0x17aa 0x2153
- end
-
- device pci 1a.0 on # USB2 EHCI
- subsystemid 0x17aa 0x2163
- end
-
- device pci 1b.0 on # Audio Controller
- subsystemid 0x17aa 0x215e
- end
-
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2 (wwan)
- device pci 1c.3 on end # PCIe Port #4 (Expresscard)
- device pci 1c.4 on end # PCIe Port #5 (wlan)
-
- device pci 1d.0 on # USB2 EHCI
- subsystemid 0x17aa 0x2163
- end
- device pci 1f.0 on # PCI-LPC bridge
- subsystemid 0x17aa 0x2166
- chip superio/nsc/pc87382
- device pnp 164e.3 on # Digitizer
- io 0x60 = 0x200
- irq 0x29 = 0xb0
- irq 0x70 = 0x5
- irq 0xf0 = 0x82
- end
- # IR, not connected
- device pnp 164e.2 off end
- # GPIO, not connected
- device pnp 164e.7 off end
- # DLPC, not connected
- device pnp 164e.19 off end
- end
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- end
- device pci 1f.2 on # IDE/SATA
- subsystemid 0x17aa 0x2168
- end
- device pci 1f.3 on # SMBUS
- subsystemid 0x17aa 0x2167
- # eeprom, 8 virtual devices, same chip
- chip drivers/i2c/at24rf08c
- device i2c 54 on end
- device i2c 55 on end
- device i2c 56 on end
- device i2c 57 on end
- device i2c 5c on end
- device i2c 5d on end
- device i2c 5e on end
- device i2c 5f on end
- end
- end
- end
- end
-end
diff --git a/src/mainboard/lenovo/t410/dock.c b/src/mainboard/lenovo/t410/dock.c
deleted file mode 100644
index 1941ac6..0000000
--- a/src/mainboard/lenovo/t410/dock.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define __SIMPLE_DEVICE__
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <delay.h>
-#include "dock.h"
-#include "southbridge/intel/ibexpeak/pch.h"
-#include "ec/lenovo/h8/h8.h"
-#include <ec/acpi/ec.h>
-
-void h8_mainboard_init_dock (void)
-{
- if (dock_present()) {
- printk(BIOS_DEBUG, "dock is connected\n");
- dock_connect();
- } else
- printk(BIOS_DEBUG, "dock is not connected\n");
-}
-
-void dock_connect(void)
-{
- u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
-
- ec_set_bit(0x02, 0);
- ec_set_bit(0x1a, 0);
- ec_set_bit(0xfe, 4);
-
- outl(inl(gpiobase + 0x0c) | (1 << 28), gpiobase + 0x0c);
-}
-
-void dock_disconnect(void)
-{
- u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
-
- ec_clr_bit(0x02, 0);
- ec_clr_bit(0x1a, 0);
- ec_clr_bit(0xfe, 4);
-
- outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c);
-}
-
-int dock_present(void)
-{
- u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
- u8 st = inb(gpiobase + 0x0c);
-
- return ((st >> 3) & 7) != 7;
-}
diff --git a/src/mainboard/lenovo/t410/dock.h b/src/mainboard/lenovo/t410/dock.h
deleted file mode 100644
index ee7aadb..0000000
--- a/src/mainboard/lenovo/t410/dock.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef THINKPAD_T410_DOCK_H
-#define THINKPAD_T410_DOCK_H
-
-void dock_connect(void);
-void dock_disconnect(void);
-int dock_present(void);
-#endif
diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl
deleted file mode 100644
index 9ee2dd1..0000000
--- a/src/mainboard/lenovo/t410/dsdt.asl
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define THINKPAD_EC_GPE 17
-#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
-#define EC_LENOVO_H8_ME_WORKAROUND 1
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x03, /* DSDT revision: ACPI v3.0 */
- "COREv4", /* OEM id */
- "COREBOOT", /* OEM table id */
- 0x20130325 /* OEM revision */
-)
-{
- /* Some generic macros */
- #include "acpi/platform.asl"
-
- /* global NVS and variables */
- #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-
- /* General Purpose Events */
- #include "acpi/gpe.asl"
-
- #include <cpu/intel/model_206ax/acpi/cpu.asl>
-
- Scope (\_SB) {
- Device (PCI0)
- {
- #include <northbridge/intel/nehalem/acpi/nehalem.asl>
- #include <southbridge/intel/bd82x6x/acpi/pch.asl>
- #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
-
- #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
- }
- Device (UNCR)
- {
- Name (_BBN, 0xFF)
- Name (_ADR, 0x00)
- Name (RID, 0x00)
- Name (_HID, EisaId ("PNP0A03"))
- Name (_CRS, ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, /* Granularity */
- 0x00FF, /* Range Minimum */
- 0x00FF, /* Range Maximum */
- 0x0000, /* Translation Offset */
- 0x0001, /* Length */
- ,, )
- })
- Device (SAD)
- {
- Name (_ADR, 0x01)
- Name (RID, 0x00)
- OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
- Field (SADC, DWordAcc, NoLock, Preserve)
- {
- Offset (0x40),
- PAM0, 8,
- PAM1, 8,
- PAM2, 8,
- PAM3, 8,
- PAM4, 8,
- PAM5, 8,
- PAM6, 8
- }
- }
- }
- }
-
-/*
- * LPC Trusted Platform Module
- */
-Scope (\_SB.PCI0.LPCB)
-{
- #include <drivers/pc80/tpm/acpi/tpm.asl>
-}
-
- /* Chipset specific sleep states */
- #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
-
- /* Dock support code */
- #include "acpi/dock.asl"
-}
diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c
deleted file mode 100644
index 820e2c5..0000000
--- a/src/mainboard/lenovo/t410/hda_verb.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Vladimir Serbinenko.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License,
- * or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */
- 0x17AA2155, /* Subsystem ID */
- 0x0000000B, /* Number of 4 dword sets */
-
- /* NID 0x01: Subsystem ID. */
- AZALIA_SUBVENDOR(0x0, 0x17AA2155),
-
- /* NID 0x19: Headphone jack. */
- AZALIA_PIN_CFG(0x0, 0x19, 0x042140F0),
-
- /* NID 0x1A: Dock mic jack. */
- AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0),
-
- /* NID 0x1B: Mic jack. */
- AZALIA_PIN_CFG(0x0, 0x1B, 0x04A190F0),
-
- /* NID 0x1C: Dock headphone jack. */
- AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0),
-
- /* NID 0x1D: EAPD detect. */
- AZALIA_PIN_CFG(0x0, 0x1D, 0x601700F0),
-
- /* NID 0x1E */
- AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0),
-
- /* NID 0x1F */
- AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0),
-
- /* NID 0x20 */
- AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0),
-
- /* NID 0x22 */
- AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0),
-
- /* NID 0x23: Internal mic boost volume. */
- AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0),
-
- 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */
- 0x17aa21b5, /* Subsystem ID */
- 0x00000004, /* Number of 4 dword sets */
-
- /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */
- AZALIA_SUBVENDOR(0x3, 0x17AA21B5),
-
- /* NID 0x04. */
- AZALIA_PIN_CFG(0x3, 0x04, 0x58560010),
-
- /* NID 0x05. */
- AZALIA_PIN_CFG(0x3, 0x05, 0x18560020),
-
- /* NID 0x06. */
- AZALIA_PIN_CFG(0x3, 0x06, 0x58560030),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/t410/mainboard.c b/src/mainboard/lenovo/t410/mainboard.c
deleted file mode 100644
index 6c5f9c9..0000000
--- a/src/mainboard/lenovo/t410/mainboard.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <delay.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <ec/lenovo/pmh7/pmh7.h>
-#include <ec/acpi/ec.h>
-#include <ec/lenovo/h8/h8.h>
-#include <northbridge/intel/nehalem/nehalem.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-
-#include <pc80/mc146818rtc.h>
-#include "dock.h"
-#include <arch/x86/include/arch/acpigen.h>
-#include <drivers/intel/gma/int15.h>
-#include <arch/interrupt.h>
-#include <pc80/keyboard.h>
-#include <cpu/x86/lapic.h>
-#include <device/pci.h>
-#include <smbios.h>
-#include "drivers/lenovo/lenovo.h"
-
-static acpi_cstate_t cst_entries[] = {
- {1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}},
- {2, 1, 500, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}},
- {2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}},
-};
-
-int get_cst_entries(acpi_cstate_t ** entries)
-{
- *entries = cst_entries;
- return ARRAY_SIZE(cst_entries);
-}
-
-static void mainboard_init(device_t dev)
-{
- printk(BIOS_SPEW, "starting SPI configuration\n");
-
- /* Configure SPI. */
- RCBA32(0x3800) = 0x07ff0500;
- RCBA32(0x3804) = 0x3f046008;
- RCBA32(0x3808) = 0x0058efc0;
- RCBA32(0x384c) = 0x92000000;
- RCBA32(0x3850) = 0x00000a0b;
- RCBA32(0x3858) = 0x07ff0500;
- RCBA32(0x385c) = 0x04ff0003;
- RCBA32(0x3860) = 0x00020001;
- RCBA32(0x3864) = 0x00000fff;
- RCBA32(0x3874) = 0;
- RCBA32(0x3890) = 0xf8400000;
- RCBA32(0x3894) = 0x143b5006;
- RCBA32(0x3898) = 0x05200302;
- RCBA32(0x389c) = 0x0601209f;
- RCBA32(0x38b0) = 0x00000004;
- RCBA32(0x38b4) = 0x03040002;
- RCBA32(0x38c8) = 0x00002005;
- RCBA32(0x38c4) = 0x00802005;
- RCBA32(0x38c0) = 0x00000007;
- RCBA32(0x3804) = 0x3f04e008;
-
- printk(BIOS_SPEW, "SPI configured\n");
-}
-
-static void fill_ssdt(device_t device)
-{
- drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0);
-}
-
-static void mainboard_enable(device_t dev)
-{
- u16 pmbase;
-
- dev->ops->init = mainboard_init;
- dev->ops->acpi_fill_ssdt_generator = fill_ssdt;
-
- pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
- PMBASE) & 0xff80;
-
- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
-
- outl(0, pmbase + SMI_EN);
-
- enable_lapic();
- pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE,
- DEFAULT_GPIOBASE | 1);
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL,
- 0x10);
-
- /* If we're resuming from suspend, blink suspend LED */
- if (acpi_is_wakeup_s3())
- ec_write(0x0c, 0xc7);
-
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2);
-
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c
deleted file mode 100644
index 20d5002..0000000
--- a/src/mainboard/lenovo/t410/romstage.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- * Copyright (C) 2013 Vladimir Serbinenko <phcoder at gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
-
-#include <stdint.h>
-#include <string.h>
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <lib.h>
-#include <pc80/mc146818rtc.h>
-#include <romstage_handoff.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <ec/acpi/ec.h>
-#include <delay.h>
-#include <timestamp.h>
-#include <arch/acpi.h>
-#include <cbmem.h>
-#include <tpm.h>
-
-#include "gpio.h"
-#include "dock.h"
-#include "arch/early_variables.h"
-#include <southbridge/intel/ibexpeak/pch.h>
-#include <northbridge/intel/nehalem/nehalem.h>
-
-#include <northbridge/intel/nehalem/raminit.h>
-#include <southbridge/intel/ibexpeak/me.h>
-
-static void pch_enable_lpc(void)
-{
- /* T410 EC Decode Range Port60/64, Port62/66 */
- /* Enable EC, PS/2 Keyboard/Mouse */
- pci_write_config16(PCH_LPC_DEV, LPC_EN,
- CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
- COMA_LPC_EN | GAMEL_LPC_EN);
-
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001);
-
- pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
-
- pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0);
- pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8);
-
- pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
- (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
-
- pci_write_config32(PCH_LPC_DEV, ETR3,
- pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
-}
-
-static void rcba_config(void)
-{
- southbridge_configure_default_intmap();
-
- static const u32 rcba_dump3[] = {
- /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
- /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
- /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,
- /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
- /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,
- /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,
- /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,
- /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,
- /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f,
- /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,
- /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,
- /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
- /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
- /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
- /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,
- /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,
- /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
- /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
- /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
- /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
- /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,
- /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000,
- /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
- };
- unsigned i;
- for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
- RCBA32(4 * i + 0x3310) = rcba_dump3[i];
- (void)RCBA32(4 * i + 0x3310);
- }
-}
-
-static inline void write_acpi32(u32 addr, u32 val)
-{
- outl(val, DEFAULT_PMBASE | addr);
-}
-
-static inline void write_acpi16(u32 addr, u16 val)
-{
- outw(val, DEFAULT_PMBASE | addr);
-}
-
-static inline u32 read_acpi32(u32 addr)
-{
- return inl(DEFAULT_PMBASE | addr);
-}
-
-static void set_fsb_frequency(void)
-{
- u8 block[5];
- u16 fsbfreq = 62879;
- smbus_block_read(0x69, 0, 5, block);
- block[0] = fsbfreq;
- block[1] = fsbfreq >> 8;
-
- smbus_block_write(0x69, 0, 5, block);
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
- u32 reg32;
- int s3resume = 0;
- const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
-
- timestamp_init(timestamp_get());
-
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (bist == 0)
- enable_lapic();
-
- nehalem_early_initialization(NEHALEM_MOBILE);
-
- pch_enable_lpc();
-
- /* Enable USB Power. We need to do it early for usbdebug to work. */
- ec_set_bit(0x3b, 4);
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&t410_gpio_map);
-
-
- /* This should probably go away. Until now it is required
- * and mainboard specific
- */
- rcba_config();
-
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* Read PM1_CNT */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
- if (((reg32 >> 10) & 7) == 5) {
- u8 reg8;
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
- printk(BIOS_DEBUG, "a2: %02x\n", reg8);
- if (!(reg8 & 0x20)) {
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
- } else {
- if (acpi_s3_resume_allowed()) {
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- s3resume = 1;
- } else {
- printk(BIOS_DEBUG,
- "Resume from S3 detected, but disabled.\n");
- }
- }
- }
-
- /* Enable SMBUS. */
- enable_smbus();
-
- outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20,
- DEFAULT_GPIOBASE | 0x3a);
- outb(0x50, 0x15ec);
- outb(inb(0x15ee) & 0x70, 0x15ee);
-
- write_acpi16(0x2, 0x0);
- write_acpi32(0x28, 0x0);
- write_acpi32(0x2c, 0x0);
- if (!s3resume) {
- read_acpi32(0x4);
- read_acpi32(0x20);
- read_acpi32(0x34);
- write_acpi16(0x0, 0x900);
- write_acpi32(0x20, 0xffff7ffe);
- write_acpi32(0x34, 0x56974);
- pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
- pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);
- }
-
- early_thermal_init();
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- chipset_init(s3resume);
-
- set_fsb_frequency();
-
- raminit(s3resume, spd_addrmap);
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- intel_early_me_status();
-
- if (s3resume) {
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- reg32 = inl(DEFAULT_PMBASE + 0x04);
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
- }
-
-
- romstage_handoff_init(s3resume);
-
- if (s3resume)
- acpi_prepare_for_resume();
- else
- quick_ram_check();
-
-#if CONFIG_LPC_TPM
- init_tpm(s3resume);
-#endif
-}
diff --git a/src/mainboard/lenovo/t410/smi.h b/src/mainboard/lenovo/t410/smi.h
deleted file mode 100644
index 4e99db9..0000000
--- a/src/mainboard/lenovo/t410/smi.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_LENOVO_X60_SMI_H
-#define MAINBOARD_LENOVO_X60_SMI_H
-
-#define SMI_DOCK_CONNECT 0x01
-#define SMI_DOCK_DISCONNECT 0x02
-
-#endif
diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c
deleted file mode 100644
index f00ae0d..0000000
--- a/src/mainboard/lenovo/t410/smihandler.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include "southbridge/intel/ibexpeak/nvs.h"
-#include "southbridge/intel/ibexpeak/pch.h"
-#include "southbridge/intel/ibexpeak/me.h"
-#include <northbridge/intel/nehalem/nehalem.h>
-#include <cpu/intel/model_2065x/model_2065x.h>
-#include <ec/acpi/ec.h>
-#include <pc80/mc146818rtc.h>
-#include <ec/lenovo/h8/h8.h>
-#include <delay.h>
-#include "dock.h"
-#include "smi.h"
-
-#define GPE_EC_SCI 1
-#define GPE_EC_WAKE 13
-
-static void mainboard_smm_init(void)
-{
- printk(BIOS_DEBUG, "initializing SMI\n");
- /* Enable 0x1600/0x1600 register pair */
- ec_set_bit(0x00, 0x05);
-}
-
-int mainboard_io_trap_handler(int smif)
-{
- static int smm_initialized;
-
- if (!smm_initialized) {
- mainboard_smm_init();
- smm_initialized = 1;
- }
-
- switch (smif) {
- case SMI_DOCK_CONNECT:
- ec_clr_bit(0x03, 2);
- udelay(250000);
- dock_connect();
- ec_set_bit(0x03, 2);
- /* set dock LED to indicate status */
- ec_write(0x0c, 0x09);
- ec_write(0x0c, 0x88);
- break;
-
- case SMI_DOCK_DISCONNECT:
- ec_clr_bit(0x03, 2);
- dock_disconnect();
- break;
-
- default:
- return 0;
- }
-
- /* On success, the IO Trap Handler returns 1
- * On failure, the IO Trap Handler returns a value != 1 */
- return 1;
-}
-
-static void mainboard_smi_brightness_up(void)
-{
- u8 value;
-
- if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
- pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
-}
-
-static void mainboard_smi_brightness_down(void)
-{
- u8 value;
-
- if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
- pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
- (value - 0x10) & 0xf0);
-}
-
-static void mainboard_smi_handle_ec_sci(void)
-{
- u8 status = inb(EC_SC);
- u8 event;
-
- if (!(status & EC_SCI_EVT))
- return;
-
- event = ec_query();
- printk(BIOS_DEBUG, "EC event %02x\n", event);
-
- switch (event) {
- case 0x14:
- /* brightness up */
- mainboard_smi_brightness_up();
- break;
- case 0x15:
- /* brightness down */
- mainboard_smi_brightness_down();
- break;
- case 0x18:
- /* Fn-F9 key */
- case 0x27:
- /* Power loss */
- case 0x50:
- /* Undock Key */
- mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
- break;
- case 0x37:
- case 0x58:
- /* Dock Event */
- mainboard_io_trap_handler(SMI_DOCK_CONNECT);
- break;
- default:
- break;
- }
-}
-
-void mainboard_smi_gpi(u32 gpi_sts)
-{
- if (gpi_sts & (1 << GPE_EC_SCI))
- mainboard_smi_handle_ec_sci();
-}
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 data)
-{
- switch (data) {
- case APM_CNT_FINALIZE:
- printk(BIOS_DEBUG, "APMC: FINALIZE\n");
- if (mainboard_finalized) {
- printk(BIOS_DEBUG, "APMC#: Already finalized\n");
- return 0;
- }
-
- intel_me_finalize_smm();
- intel_pch_finalize_smm();
- intel_nehalem_finalize_smm();
- intel_model_2065x_finalize_smm();
-
- mainboard_finalized = 1;
- break;
- case APM_CNT_ACPI_ENABLE:
- /* use 0x1600/0x1604 to prevent races with userspace */
- ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
- /* discard all events, and enable attention */
- ec_write(0x80, 0x01);
- break;
- case APM_CNT_ACPI_DISABLE:
- /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
- provide a EC query function */
- ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
- /* discard all events, and enable attention */
- ec_write(0x80, 0x01);
- break;
- default:
- break;
- }
- return 0;
-}
-
-void mainboard_smi_sleep(u8 slp_typ)
-{
- h8_usb_always_on();
-
- if (slp_typ == 3) {
- u8 ec_wake = ec_read(0x32);
- /* If EC wake events are enabled, enable wake on EC WAKE GPE. */
- if (ec_wake & 0x14) {
- /* Redirect EC WAKE GPE to SCI. */
- gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
- }
- }
-}
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I98f774b882817898815ad039efeba1d71ee98ec3
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Ani Chang <anichang at protonmail.ch>
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