[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add support for GSPI controller
Furquan Shaikh (Code Review)
gerrit at coreboot.org
Tue Apr 4 01:52:03 CEST 2017
Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19099 )
Change subject: soc/intel/skylake: Add support for GSPI controller
......................................................................
soc/intel/skylake: Add support for GSPI controller
Using the common GSPI controller driver implementation for Intel PCH,
add support for GSPI controller buses on Sky Lake / Kaby Lake.
BUG=b:35583330
Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
A src/soc/intel/skylake/gspi.c
M src/soc/intel/skylake/spi.c
4 files changed, 136 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/19099/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 8ac7263..2774e0b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -50,6 +50,7 @@
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_LPSS_I2C
@@ -113,6 +114,10 @@
int
default 120
+config SOC_INTEL_COMMON_BLOCK_GSPI_CLK_MHZ
+ int
+ default 120
+
config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM"
default 0xfef00000
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 06e1921..b31330f 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -20,6 +20,7 @@
bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
bootblock-y += gpio.c
+bootblock-y += gspi.c
bootblock-y += monotonic_timer.c
bootblock-y += pch.c
bootblock-y += pcr.c
@@ -28,6 +29,7 @@
bootblock-y += tsc_freq.c
verstage-y += flash_controller.c
+verstage-y += gspi.c
verstage-y += monotonic_timer.c
verstage-y += pch.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
@@ -39,6 +41,7 @@
romstage-y += flash_controller.c
romstage-y += gpio.c
+romstage-y += gspi.c
romstage-y += bootblock/i2c.c
romstage-y += bootblock/spi.c
romstage-y += memmap.c
@@ -65,6 +68,7 @@
ramstage-y += finalize.c
ramstage-y += flash_controller.c
ramstage-y += gpio.c
+ramstage-y += gspi.c
ramstage-y += i2c.c
ramstage-y += igd.c
ramstage-y += irq.c
diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c
new file mode 100644
index 0000000..9023f01
--- /dev/null
+++ b/src/soc/intel/skylake/gspi.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <intelblocks/gspi.h>
+#include "chip.h"
+
+#if !defined(__SIMPLE_DEVICE__)
+static struct device *spi_get_device(unsigned int bus)
+{
+ int devfn;
+
+ devfn = spi_bus_to_devfn(bus);
+ if (devfn >= 0)
+ return dev_find_slot(0, devfn);
+
+ return NULL;
+}
+
+static uintptr_t gspi_calc_base_address(unsigned int bus)
+{
+ struct resource *res;
+ struct device *dev = spi_get_device(bus);
+
+ if (!dev)
+ return 0;
+
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res)
+ return res->base;
+
+ return 0;
+}
+
+uint32_t gspi_get_bus_clk_mhz(unsigned int bus)
+{
+ struct device *dev = spi_get_device(bus);
+ struct soc_intel_skylake_config *config;
+
+ if (!dev)
+ return 0;
+
+ config = dev->chip_info;
+ if (!config)
+ return 0;
+
+ return config->spi[bus].speed_mhz;
+}
+
+#else
+
+static uintptr_t gspi_calc_base_address(unsigned int bus)
+{
+ int devfn;
+ pci_devfn_t dev;
+
+ /* Find the PCI device for this bus controller */
+ devfn = spi_bus_to_devfn(bus);
+ if (devfn < 0)
+ return 0;
+
+ /* Form a PCI address for this device */
+ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
+
+ /* Read the first base address for this device */
+ return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16);
+}
+
+uint32_t gspi_get_bus_clk_mhz(unsigned int bus)
+{
+ ROMSTAGE_CONST struct soc_intel_skylake_config *config;
+ ROMSTAGE_CONST struct device *tree_dev;
+ int devfn;
+
+ /* Find the PCI device for this bus controller */
+ devfn = spi_bus_to_devfn(bus);
+ if (devfn < 0)
+ return 0;
+
+ /* Look up the controller device in the devicetree */
+ tree_dev = dev_find_slot(0, devfn);
+ if (!tree_dev || !tree_dev->enabled)
+ return 0;
+
+ config = tree_dev->chip_info;
+ if (!config)
+ return 0;
+
+ return config->spi[bus].speed_mhz;
+}
+
+#endif
+
+/*
+ * Bus 0 is FAST SPI and we need to store base addresses for GSPI bus
+ * controllers only. Hence, the array size is set to SKYLAKE_SPI_DEV_MAX -
+ * 1. Entry 0 in the array corresponds to GSPI bus # 1 and so on.
+ */
+static uintptr_t gspi_base_address[SKYLAKE_SPI_DEV_MAX - 1] CAR_GLOBAL;
+
+uintptr_t gspi_get_bus_base_address(unsigned int bus)
+{
+ uintptr_t *base = car_get_var_ptr(gspi_base_address);
+ if (!base[bus])
+ base[bus] = gspi_calc_base_address(bus);
+ return base[bus];
+}
diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c
index 4a2ae9d..4891aca 100644
--- a/src/soc/intel/skylake/spi.c
+++ b/src/soc/intel/skylake/spi.c
@@ -20,6 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/spi.h>
+#include <intelblocks/gspi.h>
#include <soc/ramstage.h>
#include <spi-generic.h>
@@ -39,31 +40,11 @@
.setup = flash_spi_ctrlr_setup,
};
-static int gspi_ctrlr_get_config(const struct spi_slave *dev,
- struct spi_cfg *cfg)
-{
- if (dev->cs != 0) {
- printk(BIOS_ERR, "%s: Unsupported device "
- "bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs);
- return -1;
- }
-
- cfg->clk_phase = SPI_CLOCK_PHASE_FIRST;
- cfg->clk_polarity = SPI_POLARITY_LOW;
- cfg->cs_polarity = SPI_POLARITY_LOW;
- cfg->wire_mode = SPI_4_WIRE_MODE;
- cfg->data_bit_length = 8;
-
- return 0;
-}
-
-static const struct spi_ctrlr gspi_ctrlr = {
- .get_config = gspi_ctrlr_get_config,
-};
-
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{ .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
+#if !ENV_SMM
{ .ctrlr = &gspi_ctrlr, .bus_start = 1, .bus_end = 2 },
+#endif
};
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
--
To view, visit https://review.coreboot.org/19099
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I29b1d4d5a6ee4093f2596065ac375c06f17d33ac
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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