[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Get rid of redundant enable_spibar

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19097 )

Change subject: soc/intel/skylake: Get rid of redundant enable_spibar
......................................................................

soc/intel/skylake: Get rid of redundant enable_spibar

Now that we have early init enabled via spi_early_init and all
mainboards have the required early_init flag set for SPI flash, get
rid of enable_spibar which set the BAR for SPI flash.

BUG=b:35583330

Change-Id: Ia0bc6ce38aaad6161402d4c7fe14d221aba5f549
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/bootblock/pch.c
1 file changed, 0 insertions(+), 23 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/19097/1

diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 3632212..e057a4b 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -43,28 +43,6 @@
 	pci_write_config8(PCH_DEV_SPI, 0xdc, reg8);
 }
 
-static void enable_spibar(void)
-{
-	device_t dev = PCH_DEV_SPI;
-	u8 pcireg;
-
-	/* Assign Resources to SPI Controller */
-	/* Clear BIT 1-2 SPI Command Register */
-	pcireg = pci_read_config8(dev, PCI_COMMAND);
-	pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-	pci_write_config8(dev, PCI_COMMAND, pcireg);
-
-	/* Program Temporary BAR for SPI */
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0,
-		EARLY_SPI_BASE(SKYLAKE_FAST_SPI_BUS) |
-		PCI_BASE_ADDRESS_SPACE_MEMORY);
-
-	/* Enable Bus Master and MMIO Space */
-	pcireg = pci_read_config8(dev, PCI_COMMAND);
-	pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config8(dev, PCI_COMMAND, pcireg);
-}
-
 static void enable_p2sbbar(void)
 {
 	device_t dev = PCH_DEV_P2SB;
@@ -86,7 +64,6 @@
 
 void bootblock_pch_early_init(void)
 {
-	enable_spibar();
 	enable_spi_prefetch();
 	enable_p2sbbar();
 }

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia0bc6ce38aaad6161402d4c7fe14d221aba5f549
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>