[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add tsc_freq.c to verstage

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19094 )

Change subject: soc/intel/skylake: Add tsc_freq.c to verstage
......................................................................

soc/intel/skylake: Add tsc_freq.c to verstage

This is required to provide tsc freq required by timer library.

BUG=b:35583330
TEST=Verified that delay(5) in verstage adds a delay of 5 seconds.

Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/19094/1

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index f7b4971..f9c267e 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -33,6 +33,7 @@
 verstage-y += pmutil.c
 verstage-y += bootblock/i2c.c
 verstage-y += spi.c
+verstage-y += tsc_freq.c
 
 romstage-y += flash_controller.c
 romstage-y += gpio.c

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>