[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Allow mainboards to pass in SPI config
Furquan Shaikh (Code Review)
gerrit at coreboot.org
Tue Apr 4 01:52:00 CEST 2017
Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19095 )
Change subject: soc/intel/skylake: Allow mainboards to pass in SPI config
......................................................................
soc/intel/skylake: Allow mainboards to pass in SPI config
Similar to I2C, allow mainboards to pass in SPI config details:
1. early_init - If BAR for the controller needs to be initialized
before memory is up.
2. speed_mhz - Desired speed of the SPI bus in MHz.
Provide spi_early_init function that looks up device tree config and
decides if BAR needs to be set up for the controller. Provide macros
for FAST_SPI_BUS and GSPI*_BUS to make it easier to refer to a
particular bus.
BUG=b:35583330
Change-Id: I18844e2e3fc862006df072444f397d31e091e3fd
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/cpu.c
M src/soc/intel/skylake/bootblock/pch.c
A src/soc/intel/skylake/bootblock/spi.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/include/soc/bootblock.h
M src/soc/intel/skylake/include/soc/iomap.h
M src/soc/intel/skylake/include/soc/pci_devs.h
9 files changed, 99 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/19095/1
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index f9c267e..06e1921 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -15,6 +15,7 @@
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += bootblock/smbus.c
+bootblock-y += bootblock/spi.c
bootblock-y += flash_controller.c
bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
@@ -32,12 +33,14 @@
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
verstage-y += pmutil.c
verstage-y += bootblock/i2c.c
+verstage-y += bootblock/spi.c
verstage-y += spi.c
verstage-y += tsc_freq.c
romstage-y += flash_controller.c
romstage-y += gpio.c
romstage-y += bootblock/i2c.c
+romstage-y += bootblock/spi.c
romstage-y += memmap.c
romstage-y += monotonic_timer.c
romstage-y += me.c
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index c11d3d2..f060269 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -25,6 +25,7 @@
void bootblock_soc_early_init(void)
{
bootblock_systemagent_early_init();
+ spi_early_init();
bootblock_pch_early_init();
bootblock_cpu_init();
pch_early_iorange_init();
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index fab589f..b9e6b55 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -36,7 +36,7 @@
static void set_pch_cpu_strap(u8 flex_ratio)
{
- uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
+ uint8_t *spibar = (void *)EARLY_SPI_BASE(SKYLAKE_FAST_SPI_BUS);
u32 ssl, ssms, soft_reset_data;
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 60b22dc..3632212 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -56,7 +56,8 @@
/* Program Temporary BAR for SPI */
pci_write_config32(dev, PCI_BASE_ADDRESS_0,
- SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
+ EARLY_SPI_BASE(SKYLAKE_FAST_SPI_BUS) |
+ PCI_BASE_ADDRESS_SPACE_MEMORY);
/* Enable Bus Master and MMIO Space */
pcireg = pci_read_config8(dev, PCI_COMMAND);
diff --git a/src/soc/intel/skylake/bootblock/spi.c b/src/soc/intel/skylake/bootblock/spi.c
new file mode 100644
index 0000000..c4fdcaa
--- /dev/null
+++ b/src/soc/intel/skylake/bootblock/spi.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <soc/bootblock.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include "chip.h"
+
+static void spi_early_init_bus(unsigned int bus)
+{
+ ROMSTAGE_CONST struct soc_intel_skylake_config *config;
+ ROMSTAGE_CONST struct device *tree_dev;
+ pci_devfn_t dev;
+ int devfn;
+ uintptr_t base;
+
+ /* Find the PCI device for this bus controller */
+ devfn = spi_bus_to_devfn(bus);
+ if (devfn < 0)
+ return;
+
+ /* Look up the controller device in the devicetree */
+ tree_dev = dev_find_slot(0, devfn);
+ if (!tree_dev || !tree_dev->enabled)
+ return;
+
+ /* Skip if not enabled for early init */
+ config = tree_dev->chip_info;
+ if (!config)
+ return;
+ if (!config->spi[bus].early_init)
+ return;
+
+ /* Prepare early base address for access before memory */
+ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
+ base = EARLY_SPI_BASE(bus);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
+ pci_write_config32(dev, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+}
+
+void spi_early_init(void)
+{
+ int bus;
+
+ /* Initialize SPI controllers that are enabled in devicetree. */
+ for (bus = 0; bus < SKYLAKE_SPI_DEV_MAX; bus++)
+ spi_early_init_bus(bus);
+}
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 85857d8..0e9bbf9 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -24,6 +24,7 @@
#include <stdint.h>
#include <soc/gpio_defs.h>
#include <soc/gpe.h>
+#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/intel/common/lpss_i2c.h>
#include <soc/pci_devs.h>
@@ -33,6 +34,7 @@
#include <soc/vr_config.h>
#define SKYLAKE_I2C_DEV_MAX 6
+#define SKYLAKE_SPI_DEV_MAX 3
enum skylake_i2c_voltage {
I2C_VOLTAGE_3V3,
@@ -46,6 +48,13 @@
int early_init;
/* Custom bus speed configuration { scl_lcnt, scl_hcnt, sda_hold } */
struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT];
+};
+
+struct skylake_spi_config {
+ /* Bus speed in MHz. */
+ uint32_t speed_mhz;
+ /* Bus should be enabled prior to ramstage with temporary base. */
+ uint8_t early_init;
};
struct soc_intel_skylake_config {
@@ -208,6 +217,9 @@
enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX];
struct lpss_i2c_bus_config i2c[SKYLAKE_I2C_DEV_MAX];
+ /* SPI */
+ struct skylake_spi_config spi[SKYLAKE_SPI_DEV_MAX];
+
/* Camera */
u8 Cio2Enable;
u8 SaImguEnable;
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index f290d0f..680fc15 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -26,6 +26,7 @@
/* Bootblock pre console init programing */
void bootblock_cpu_init(void);
+void spi_early_init(void);
void bootblock_pch_early_init(void);
void pch_uart_init(void);
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index a6f7287..c47cea9 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -32,6 +32,12 @@
#define EARLY_I2C_BASE_ADDRESS 0xfe040000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+#define EARLY_SPI_BASE_ADDRESS 0xfe010000
+#define EARLY_SPI_BASE(x) (EARLY_SPI_BASE_ADDRESS + (0x1000 * (x)))
+#define SKYLAKE_FAST_SPI_BUS 0
+#define SKYLAKE_GSPI0_BUS 1
+#define SKYLAKE_GSPI1_BUS 2
+
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE 0x8000
@@ -51,8 +57,6 @@
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_SIZE 0x10000
-
-#define SPI_BASE_ADDRESS 0xfe010000
#define GPIO_BASE_SIZE 0x10000
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 469d7e9..13114f1 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -186,4 +186,14 @@
return -1;
}
+static inline int spi_bus_to_devfn(unsigned int bus)
+{
+ switch (bus) {
+ case 0: return PCH_DEVFN_SPI;
+ case 1: return PCH_DEVFN_GSPI0;
+ case 2: return PCH_DEVFN_GSPI1;
+ }
+ return -1;
+}
+
#endif
--
To view, visit https://review.coreboot.org/19095
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I18844e2e3fc862006df072444f397d31e091e3fd
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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