[coreboot-gerrit] Change in coreboot[master]: amd/pi: Add verstage support

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/18439 )

Change subject: amd/pi: Add verstage support
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Patch Set 7:

(2 comments)

https://review.coreboot.org/#/c/18439/7/src/cpu/amd/pi/romstage_after_verstage.S
File src/cpu/amd/pi/romstage_after_verstage.S:

Line 21: 	call	romstage_after_verstage
> If the above never returns how did you tear down CAR in after_raminit.S? We
The CAR teardown code is called, not returned to: car.c/romstage_after_verstage(), romstage.c/cache_as_ram_stage_main(), which calls disable_cache_as_ram() located in the include below.


Line 23: 	#include "after_raminit.S"
> Is there a reason why arch/x86/assembly_entry.S isn't being utilized for th
I'm not sure I follow you.  That file's included in the build by early_x86_assembly_entry_rule and is being used.  The only car_stage_entry there is a weak jmp $, and the ROMSTAGE_AFTER_VERSTAGE check seems to be working properly.

FWIW, it looks like the FSP1.1/SKL example has changed since we first added this.
https://review.coreboot.org/#/c/17976
We don't have the same build problems, however.  We build/run regardless of SEPARATE_VERSTAGE.


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Gerrit-MessageType: comment
Gerrit-Change-Id: Ie43d87908c2d83b42b95b306419156e85993f7bd
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
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