[coreboot-gerrit] Change in coreboot[master]: nb/intel/gma: Implement and use common VBT implementation
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Mon Apr 3 18:33:00 CEST 2017
Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19084 )
Change subject: nb/intel/gma: Implement and use common VBT implementation
......................................................................
nb/intel/gma: Implement and use common VBT implementation
Implement a common ACPI IGD OpRegion function.
Remove all northbridge duplicates.
Retrieve IGD OpRegion base address through a function.
Split ASLS and SCIS into two functions.
Tested on GM45 (Lenovo T500).
Change-Id: Ib1c60a317ecfdd3189558b53018258eceb0f4955
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/drivers/intel/gma/i915.h
M src/drivers/intel/gma/vbt.c
M src/northbridge/intel/fsp_sandybridge/acpi.c
M src/northbridge/intel/fsp_sandybridge/northbridge.h
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/haswell.h
M src/northbridge/intel/i945/acpi.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/nehalem/acpi.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/nehalem.h
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/acpi.c
M src/northbridge/intel/sandybridge/sandybridge.h
M src/northbridge/intel/x4x/acpi.c
M src/northbridge/intel/x4x/gma.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/fsp_bd82x6x/lpc.c
M src/southbridge/intel/fsp_i89xx/lpc.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
23 files changed, 212 insertions(+), 590 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/19084/1
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index d9bb940..4482eb5 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -298,7 +298,6 @@
int i915lightup(unsigned int physbase, unsigned int mmio,
unsigned int gfx, unsigned int init_fb);
int panel_lightup(struct intel_dp *dp, unsigned int init_fb);
-void *igd_make_opregion(void);
/* display.c */
void compute_display_params(struct intel_dp *dp);
@@ -309,6 +308,11 @@
generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf,
struct device *dev, const char *idstr);
+void intel_gma_setup_asls(struct device *igd);
+u32 intel_gma_get_asls(void);
+int intel_gma_init_igd_opregion(struct device *dev);
+void intel_gma_setup_scis(struct device *igd);
+
/* interface to libgfxinit (gma.adb) */
void gma_gfxinit(u64 mmio_base, u64 linear_fb, u32 phys_fb, int *success);
diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c
index c908eb4..58d63da 100644
--- a/src/drivers/intel/gma/vbt.c
+++ b/src/drivers/intel/gma/vbt.c
@@ -22,9 +22,19 @@
#include <string.h>
#include <device/pci.h>
#include <drivers/intel/gma/opregion.h>
+#include <device/pci_ids.h>
+#include <device/pci_rom.h>
+#include <cbmem.h>
#include "i915.h"
#include "intel_bios.h"
+
+#define TCO1_STS 0x64
+#define DMISCI_STS (1 << 9)
+#define GPE0_STS 0x20
+#define TCOSCI_STS (1 << 6)
+#define GPE0_EN 0x2c
+#define TCOSCI_EN (1 << 6)
static size_t generate_vbt(const struct i915_gpu_controller_info *const conf,
struct vbt_header *const head,
@@ -105,3 +115,146 @@
oh->size = fake_oprom_size;
pcir->imagelength = fake_oprom_size;
}
+
+static void *validate_intel_oprom(u8 *vbios)
+{
+ optionrom_header_t *oprom = (optionrom_header_t *)vbios;
+ optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
+ oprom->pcir_offset);
+
+ printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
+ oprom->signature, pcir->vendor, pcir->classcode[0],
+ pcir->classcode[1], pcir->classcode[2]);
+
+ if ((oprom->signature == OPROM_SIGNATURE) &&
+ (pcir->vendor == PCI_VENDOR_ID_INTEL) &&
+ (pcir->classcode[0] == 0x00) &&
+ (pcir->classcode[1] == 0x00) &&
+ (pcir->classcode[2] == 0x03))
+ return (void *)vbios;
+
+ return NULL;
+}
+
+static int init_opregion_vbt(struct device *dev, igd_opregion_t *opregion)
+{
+ void *vbios = NULL;
+ printk(BIOS_DEBUG, "Init IGD OpRegion.\n");
+
+ if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+ vbios = validate_intel_oprom((void *)PCI_VGA_RAM_IMAGE_START);
+ if (!vbios)
+ vbios = validate_intel_oprom((void *)pci_rom_probe(dev));
+
+ printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
+ optionrom_header_t *oprom = (optionrom_header_t *)vbios;
+ optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
+ oprom->vbt_offset);
+
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
+ printk(BIOS_DEBUG, "VBT not found!\n");
+ return 1;
+ }
+
+ memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
+ memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
+ vbt->hdr_vbt_size : 7168);
+
+ return 0;
+}
+
+/* Initialize IGD OpRegion, called from ACPI code */
+int intel_gma_init_igd_opregion(struct device *dev)
+{
+ igd_opregion_t *opregion;
+
+ opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
+ if (!opregion)
+ return 1;
+
+ memset((void *)opregion, 0, sizeof(igd_opregion_t));
+
+ memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+ sizeof(opregion->header.signature));
+
+ /* 8kb */
+ opregion->header.size = sizeof(igd_opregion_t) / 1024;
+ opregion->header.version = IGD_OPREGION_VERSION;
+
+ // FIXME We just assume we're mobile for now
+ opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+ // TODO Initialize Mailbox 1
+
+ // TODO Initialize Mailbox 3
+ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
+ opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
+ opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
+ opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
+ opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
+ opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
+ opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
+ opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
+ opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
+ opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
+ opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
+ opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
+ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
+ opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
+ opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
+
+ return init_opregion_vbt(dev, opregion);
+}
+
+u32 intel_gma_get_asls(void)
+{
+ void *ptr = cbmem_find(CBMEM_ID_IGD_OPREGION);
+
+ if (ptr)
+ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
+
+ return (u32)ptr;
+}
+
+void intel_gma_setup_asls(struct device *igd)
+{
+ igd_opregion_t *opregion;
+ u16 reg16;
+
+ if (!igd->enabled)
+ return;
+
+ opregion = cbmem_find(CBMEM_ID_IGD_OPREGION);
+ if (!opregion)
+ return;
+
+ pci_write_config32(igd, ASLS, (u32)opregion);
+ reg16 = pci_read_config16(igd, SWSCI);
+ reg16 &= ~(1 << 0);
+ reg16 |= (1 << 15);
+ pci_write_config16(igd, SWSCI, reg16);
+}
+
+void intel_gma_setup_scis(struct device *igd)
+{
+ u16 reg16, pmbase;
+
+ if (!igd->enabled)
+ return;
+
+ pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+ 0x40) & 0xfffc;
+
+ /* clear dmisci status */
+ reg16 = inw(pmbase + TCO1_STS);
+ reg16 |= DMISCI_STS; // reference code does an &=
+ outw(pmbase + TCO1_STS, reg16);
+
+ /* clear acpi tco status */
+ outl(pmbase + GPE0_STS, TCOSCI_STS);
+
+ /* enable acpi tco scis */
+ reg16 = inw(pmbase + GPE0_EN);
+ reg16 |= TCOSCI_EN;
+ outw(pmbase + GPE0_EN, reg16);
+}
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c
index a30cb7a..a621276 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi.c
+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c
@@ -16,18 +16,11 @@
*/
#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <arch/io.h>
#include <arch/acpi.h>
-#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <drivers/intel/gma/i915.h>
#include <arch/acpigen.h>
#include "northbridge.h"
-#include <cbmem.h>
-#include <drivers/intel/gma/intel_bios.h>
unsigned long acpi_fill_mcfg(unsigned long current)
{
@@ -72,138 +65,4 @@
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
-}
-
-static void *get_intel_vbios(void)
-{
- /* This should probably be looking at CBFS or we should always
- * deploy the VBIOS on Intel systems, even if we don't run it
- * in coreboot (e.g. SeaBIOS only scenarios).
- */
- u8 *vbios = (u8 *)0xc0000;
-
- optionrom_header_t *oprom = (optionrom_header_t *)vbios;
- optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
- oprom->pcir_offset);
-
-
- printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
- oprom->signature, pcir->vendor, pcir->classcode[0],
- pcir->classcode[1], pcir->classcode[2]);
-
-
- if ((oprom->signature == OPROM_SIGNATURE) &&
- (pcir->vendor == PCI_VENDOR_ID_INTEL) &&
- (pcir->classcode[0] == 0x00) &&
- (pcir->classcode[1] == 0x00) &&
- (pcir->classcode[2] == 0x03))
- return (void *)vbios;
-
- return NULL;
-}
-
-static int init_opregion_vbt(igd_opregion_t *opregion)
-{
- void *vbios;
- vbios = get_intel_vbios();
- if (!vbios) {
- printk(BIOS_DEBUG, "VBIOS not found.\n");
- return 1;
- }
-
- printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
- optionrom_header_t *oprom = (optionrom_header_t *)vbios;
- optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
- oprom->vbt_offset);
-
- if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
- printk(BIOS_DEBUG, "VBT not found!\n");
- return 1;
- }
-
- memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
- memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
- vbt->hdr_vbt_size : 7168);
-
- return 0;
-}
-
-
-/* Initialize IGD OpRegion, called from ACPI code */
-int init_igd_opregion(igd_opregion_t *opregion)
-{
- device_t igd;
- u16 reg16;
-
- memset((void *)opregion, 0, sizeof(igd_opregion_t));
-
- // FIXME if IGD is disabled, we should exit here.
-
- memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
- sizeof(opregion->header.signature));
-
- /* 8kb */
- opregion->header.size = sizeof(igd_opregion_t) / 1024;
- opregion->header.version = IGD_OPREGION_VERSION;
-
- // FIXME We just assume we're mobile for now
- opregion->header.mailboxes = MAILBOXES_MOBILE;
-
- // TODO Initialize Mailbox 1
-
- // TODO Initialize Mailbox 3
- opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
- opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
- opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
- opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
- opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
- opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
- opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
- opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
- opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
- opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
- opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
- opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
- opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
- opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
- opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
-
- init_opregion_vbt(opregion);
-
- /* TODO This needs to happen in S3 resume, too.
- * Maybe it should move to the finalize handler
- */
- igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
-
- pci_write_config32(igd, ASLS, (u32)opregion);
- reg16 = pci_read_config16(igd, SWSCI);
- reg16 &= ~(1 << 0);
- reg16 |= (1 << 15);
- pci_write_config16(igd, SWSCI, reg16);
-
- /* clear dmisci status */
- reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
- reg16 |= DMISCI_STS; // reference code does an &=
- outw(DEFAULT_PMBASE + TCO1_STS, reg16);
-
- /* clear acpi tco status */
- outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
-
- /* enable acpi tco scis */
- reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
- reg16 |= TCOSCI_EN;
- outw(DEFAULT_PMBASE + GPE0_EN, reg16);
-
- return 0;
-}
-
-void *igd_make_opregion(void)
-{
- igd_opregion_t *opregion;
-
- printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
- opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
- if (opregion)
- init_igd_opregion(opregion);
- return opregion;
}
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index 0be01cc..c0194f2 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -215,11 +215,6 @@
void report_platform_info(void);
#endif /* !__SMM__ */
-#if !defined(__PRE_RAM__)
-#include <drivers/intel/gma/opregion.h>
-int init_igd_opregion(igd_opregion_t *igd_opregion);
-#endif
-
#endif
#endif
#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index cbb8451..0d04f33 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -732,6 +732,14 @@
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA");
}
+
+ /* Setup VBT for ACPI */
+ if (intel_gma_init_igd_opregion(dev)) {
+ printk(BIOS_ERR, "Failed to setup VBT.\n");
+ return;
+ }
+ intel_gma_setup_asls(dev);
+ intel_gma_setup_scis(dev);
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index cb430f9..2615115 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -16,18 +16,10 @@
*/
#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <arch/io.h>
#include <arch/acpi.h>
-#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
#include "haswell.h"
-#include <cbmem.h>
#include <arch/acpigen.h>
-#include <cpu/cpu.h>
-#include <drivers/intel/gma/intel_bios.h>
unsigned long acpi_fill_mcfg(unsigned long current)
{
@@ -70,122 +62,4 @@
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
-}
-
-static void *get_intel_vbios(void)
-{
- /* This should probably be looking at CBFS or we should always
- * deploy the VBIOS on Intel systems, even if we don't run it
- * in coreboot (e.g. SeaBIOS only scenarios).
- */
- u8 *vbios = (u8 *)0xc0000;
-
- optionrom_header_t *oprom = (optionrom_header_t *)vbios;
- optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
- oprom->pcir_offset);
-
-
- printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
- oprom->signature, pcir->vendor, pcir->classcode[0],
- pcir->classcode[1], pcir->classcode[2]);
-
-
- if ((oprom->signature == OPROM_SIGNATURE) &&
- (pcir->vendor == PCI_VENDOR_ID_INTEL) &&
- (pcir->classcode[0] == 0x00) &&
- (pcir->classcode[1] == 0x00) &&
- (pcir->classcode[2] == 0x03))
- return (void *)vbios;
-
- return NULL;
-}
-
-static int init_opregion_vbt(igd_opregion_t *opregion)
-{
- void *vbios;
- vbios = get_intel_vbios();
- if (!vbios) {
- printk(BIOS_DEBUG, "VBIOS not found.\n");
- return 1;
- }
-
- printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
- optionrom_header_t *oprom = (optionrom_header_t *)vbios;
- optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
- oprom->vbt_offset);
-
- if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
- printk(BIOS_DEBUG, "VBT not found!\n");
- return 1;
- }
-
- memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
- memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
- vbt->hdr_vbt_size : 7168);
-
- return 0;
-}
-
-
-/* Initialize IGD OpRegion, called from ACPI code */
-int init_igd_opregion(igd_opregion_t *opregion)
-{
- device_t igd;
- u16 reg16;
-
- memset((void *)opregion, 0, sizeof(igd_opregion_t));
-
- // FIXME if IGD is disabled, we should exit here.
-
- memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
- sizeof(opregion->header.signature));
-
- /* 8kb */
- opregion->header.size = sizeof(igd_opregion_t) / 1024;
- opregion->header.version = IGD_OPREGION_VERSION;
-
- // FIXME We just assume we're mobile for now
- opregion->header.mailboxes = MAILBOXES_MOBILE;
-
- // TODO Initialize Mailbox 1
-
- // TODO Initialize Mailbox 3
- opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
- opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
- opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
- opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
- opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
- opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
- opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
- opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
- opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
- opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
- opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
- opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
- opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
- opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
- opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
-
- init_opregion_vbt(opregion);
-
- /* TODO This needs to happen in S3 resume, too.
- * Maybe it should move to the finalize handler
- */
- igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
-
- pci_write_config32(igd, ASLS, (u32)opregion);
- reg16 = pci_read_config16(igd, SWSCI);
- reg16 &= ~(1 << 0);
- reg16 |= (1 << 15);
- pci_write_config16(igd, SWSCI, reg16);
-
- /* clear dmisci status */
- reg16 = inw(get_pmbase() + TCO1_STS);
- reg16 |= DMISCI_STS; // reference code does an &=
- outw(get_pmbase() + TCO1_STS, reg16);
-
- /* clear and enable ACPI TCO SCI */
- enable_tco_sci();
-
- return 0;
}
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 31e3cb6..6753dba 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -476,6 +476,14 @@
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
+
+ /* Setup VBT for ACPI */
+ if (intel_gma_init_igd_opregion(dev)) {
+ printk(BIOS_ERR, "Failed to setup VBT.\n");
+ return;
+ }
+ intel_gma_setup_asls(dev);
+ intel_gma_setup_scis(dev);
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index f0fe07d..00616af 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -213,11 +213,6 @@
void report_platform_info(void);
#endif /* !__SMM__ */
-#if !defined(__PRE_RAM__)
-#include <drivers/intel/gma/opregion.h>
-int init_igd_opregion(igd_opregion_t *igd_opregion);
-#endif
-
#endif
#endif
#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index c1a3d17..79e2d8f 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -16,13 +16,11 @@
#include <types.h>
#include <string.h>
-#include <console/console.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <cbmem.h>
#include <arch/acpigen.h>
#include <cpu/cpu.h>
#include "i945.h"
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 0765767..710827a 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -686,6 +686,14 @@
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
}
+
+ /* Setup VBT for ACPI */
+ if (intel_gma_init_igd_opregion(dev)) {
+ printk(BIOS_ERR, "Failed to setup VBT.\n");
+ return;
+ }
+ intel_gma_setup_asls(dev);
+ intel_gma_setup_scis(dev);
}
/* This doesn't reclaim stolen UMA memory, but IGD could still
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 1a02e7b..46405ee 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -19,18 +19,10 @@
#define __SIMPLE_DEVICE__
#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <arch/io.h>
#include <arch/acpi.h>
-#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <drivers/intel/gma/intel_bios.h>
#include <arch/acpigen.h>
-#include <cpu/cpu.h>
-#include <drivers/intel/gma/i915.h>
-#include <cbmem.h>
#include "nehalem.h"
unsigned long acpi_fill_mcfg(unsigned long current)
@@ -75,133 +67,4 @@
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
-}
-
-static void *get_intel_vbios(void)
-{
- /* This should probably be looking at CBFS or we should always
- * deploy the VBIOS on Intel systems, even if we don't run it
- * in coreboot (e.g. SeaBIOS only scenarios).
- */
- u8 *vbios = (u8 *) 0xc0000;
-
- optionrom_header_t *oprom = (optionrom_header_t *) vbios;
- optionrom_pcir_t *pcir = (optionrom_pcir_t *) (vbios +
- oprom->pcir_offset);
-
- printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
- oprom->signature, pcir->vendor, pcir->classcode[0],
- pcir->classcode[1], pcir->classcode[2]);
-
- if ((oprom->signature == OPROM_SIGNATURE) &&
- (pcir->vendor == PCI_VENDOR_ID_INTEL) &&
- (pcir->classcode[0] == 0x00) &&
- (pcir->classcode[1] == 0x00) && (pcir->classcode[2] == 0x03))
- return (void *)vbios;
-
- return NULL;
-}
-
-static int init_opregion_vbt(igd_opregion_t * opregion)
-{
- void *vbios;
- vbios = get_intel_vbios();
- if (!vbios) {
- printk(BIOS_DEBUG, "VBIOS not found.\n");
- return 1;
- }
-
- printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
- optionrom_header_t *oprom = (optionrom_header_t *) vbios;
- optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
-
- if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
- printk(BIOS_DEBUG, "VBT not found!\n");
- return 1;
- }
-
- memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
- memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
- vbt->hdr_vbt_size : 7168);
-
- return 0;
-}
-
-/* Initialize IGD OpRegion, called from ACPI code */
-int init_igd_opregion(igd_opregion_t * opregion)
-{
- pci_devfn_t igd;
- u16 reg16;
-
- memset((void *)opregion, 0, sizeof(igd_opregion_t));
-
- // FIXME if IGD is disabled, we should exit here.
-
- memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
- sizeof(opregion->header.signature));
-
- /* 8kb */
- opregion->header.size = sizeof(igd_opregion_t) / 1024;
- opregion->header.version = IGD_OPREGION_VERSION;
-
- // FIXME We just assume we're mobile for now
- opregion->header.mailboxes = MAILBOXES_MOBILE;
-
- // TODO Initialize Mailbox 1
-
- // TODO Initialize Mailbox 3
- opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
- opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
- opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
- opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
- opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
- opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
- opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
- opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
- opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
- opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
- opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
- opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
- opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
- opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
- opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
-
- init_opregion_vbt(opregion);
-
- /* TODO This needs to happen in S3 resume, too.
- * Maybe it should move to the finalize handler
- */
- igd = PCI_DEV(0, 0x2, 0);
-
- pci_write_config32(igd, ASLS, (u32) opregion);
- reg16 = pci_read_config16(igd, SWSCI);
- reg16 &= ~(1 << 0);
- reg16 |= (1 << 15);
- pci_write_config16(igd, SWSCI, reg16);
-
- /* clear dmisci status */
- reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
- reg16 |= DMISCI_STS; // reference code does an &=
- outw(DEFAULT_PMBASE + TCO1_STS, reg16);
-
- /* clear acpi tco status */
- outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
-
- /* enable acpi tco scis */
- reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
- reg16 |= TCOSCI_EN;
- outw(DEFAULT_PMBASE + GPE0_EN, reg16);
-
- return 0;
-}
-
-void *igd_make_opregion(void)
-{
- igd_opregion_t *opregion;
-
- printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
- opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
- if (opregion)
- init_igd_opregion(opregion);
- return opregion;
}
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index 4e57b0f..1ec2367 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -1038,9 +1038,16 @@
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
#endif
-
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
+
+ /* Setup VBT for ACPI */
+ if (intel_gma_init_igd_opregion(dev)) {
+ printk(BIOS_ERR, "Failed to setup VBT.\n");
+ return;
+ }
+ intel_gma_setup_asls(dev);
+ intel_gma_setup_scis(dev);
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 5385b8e..a693e12 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -300,11 +300,6 @@
void report_platform_info(void);
#endif /* !__SMM__ */
-#if !defined(__PRE_RAM__)
-#include <drivers/intel/gma/opregion.h>
-int init_igd_opregion(igd_opregion_t *igd_opregion);
-#endif
-
#endif
#endif
#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index c92428e..32cb7ca 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -278,6 +278,14 @@
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW");
}
+
+ /* Setup VBT for ACPI */
+ if (intel_gma_init_igd_opregion(dev)) {
+ printk(BIOS_ERR, "Failed to setup VBT.\n");
+ return;
+ }
+ intel_gma_setup_asls(dev);
+ intel_gma_setup_scis(dev);
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index e696ac7..586fa32 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -16,19 +16,12 @@
*/
#include <types.h>
-#include <string.h>
#include <console/console.h>
-#include <arch/io.h>
#include <arch/acpi.h>
-#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <drivers/intel/gma/i915.h>
#include <arch/acpigen.h>
#include "sandybridge.h"
-#include <cbmem.h>
-#include <drivers/intel/gma/intel_bios.h>
-#include <southbridge/intel/bd82x6x/pch.h>
unsigned long acpi_fill_mcfg(unsigned long current)
{
@@ -73,140 +66,6 @@
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
-}
-
-static void *get_intel_vbios(void)
-{
- /* This should probably be looking at CBFS or we should always
- * deploy the VBIOS on Intel systems, even if we don't run it
- * in coreboot (e.g. SeaBIOS only scenarios).
- */
- u8 *vbios = (u8 *)0xc0000;
-
- optionrom_header_t *oprom = (optionrom_header_t *)vbios;
- optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
- oprom->pcir_offset);
-
-
- printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
- oprom->signature, pcir->vendor, pcir->classcode[0],
- pcir->classcode[1], pcir->classcode[2]);
-
-
- if ((oprom->signature == OPROM_SIGNATURE) &&
- (pcir->vendor == PCI_VENDOR_ID_INTEL) &&
- (pcir->classcode[0] == 0x00) &&
- (pcir->classcode[1] == 0x00) &&
- (pcir->classcode[2] == 0x03))
- return (void *)vbios;
-
- return NULL;
-}
-
-static int init_opregion_vbt(igd_opregion_t *opregion)
-{
- void *vbios;
- vbios = get_intel_vbios();
- if (!vbios) {
- printk(BIOS_DEBUG, "VBIOS not found.\n");
- return 1;
- }
-
- printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
- optionrom_header_t *oprom = (optionrom_header_t *)vbios;
- optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
- oprom->vbt_offset);
-
- if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
- printk(BIOS_DEBUG, "VBT not found!\n");
- return 1;
- }
-
- memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
- memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
- vbt->hdr_vbt_size : 7168);
-
- return 0;
-}
-
-
-/* Initialize IGD OpRegion, called from ACPI code */
-int init_igd_opregion(igd_opregion_t *opregion)
-{
- device_t igd;
- u16 reg16;
-
- memset((void *)opregion, 0, sizeof(igd_opregion_t));
-
- // FIXME if IGD is disabled, we should exit here.
-
- memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
- sizeof(opregion->header.signature));
-
- /* 8kb */
- opregion->header.size = sizeof(igd_opregion_t) / 1024;
- opregion->header.version = IGD_OPREGION_VERSION;
-
- // FIXME We just assume we're mobile for now
- opregion->header.mailboxes = MAILBOXES_MOBILE;
-
- // TODO Initialize Mailbox 1
-
- // TODO Initialize Mailbox 3
- opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
- opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
- opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
- opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
- opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
- opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
- opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
- opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
- opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
- opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
- opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
- opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
- opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
- opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
- opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
-
- init_opregion_vbt(opregion);
-
- /* TODO This needs to happen in S3 resume, too.
- * Maybe it should move to the finalize handler
- */
- igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
-
- pci_write_config32(igd, ASLS, (u32)opregion);
- reg16 = pci_read_config16(igd, SWSCI);
- reg16 &= ~(1 << 0);
- reg16 |= (1 << 15);
- pci_write_config16(igd, SWSCI, reg16);
-
- /* clear dmisci status */
- reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
- reg16 |= DMISCI_STS; // reference code does an &=
- outw(DEFAULT_PMBASE + TCO1_STS, reg16);
-
- /* clear acpi tco status */
- outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
-
- /* enable acpi tco scis */
- reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
- reg16 |= TCOSCI_EN;
- outw(DEFAULT_PMBASE + GPE0_EN, reg16);
-
- return 0;
-}
-
-void *igd_make_opregion(void)
-{
- igd_opregion_t *opregion;
-
- printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
- opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
- if (opregion)
- init_igd_opregion(opregion);
- return opregion;
}
static unsigned long acpi_fill_dmar(unsigned long current)
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 8d2ae85..1f27e3c 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -235,11 +235,6 @@
unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp);
#endif
-#if !defined(__PRE_RAM__)
-#include <drivers/intel/gma/opregion.h>
-int init_igd_opregion(igd_opregion_t *igd_opregion);
-#endif
-
#endif
#endif
#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */
diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c
index 21f7aa9..45e76e0 100644
--- a/src/northbridge/intel/x4x/acpi.c
+++ b/src/northbridge/intel/x4x/acpi.c
@@ -23,7 +23,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <cbmem.h>
#include <arch/acpigen.h>
#include <cpu/cpu.h>
#include "x4x.h"
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index f4b2b2e..0203f48 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -374,6 +374,14 @@
native_init(dev);
else
pci_dev_init(dev);
+
+ /* Setup VBT for ACPI */
+ if (intel_gma_init_igd_opregion(dev)) {
+ printk(BIOS_ERR, "Failed to setup VBT.\n");
+ return;
+ }
+ intel_gma_setup_asls(dev);
+ intel_gma_setup_scis(dev);
}
static void gma_set_subsystem(device_t dev, unsigned int vendor,
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 623482e..35588e9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -654,10 +654,6 @@
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -677,7 +673,7 @@
#endif
/* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
+ gnvs->aslb = intel_gma_get_asls();
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index c2dea6b..03178ec 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -589,10 +589,6 @@
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -601,7 +597,7 @@
acpi_create_gnvs(gnvs);
/* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
+ gnvs->aslb = intel_gma_get_asls();
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c
index 7ebe6e4..2371008 100644
--- a/src/southbridge/intel/fsp_i89xx/lpc.c
+++ b/src/southbridge/intel/fsp_i89xx/lpc.c
@@ -501,10 +501,6 @@
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -513,7 +509,7 @@
acpi_create_gnvs(gnvs);
/* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
+ gnvs->aslb = intel_gma_get_asls();
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 8212b0a..b5134a5 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -548,6 +548,8 @@
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
+ /* IGD OpRegion Base Address */
+ gnvs->aslb = intel_gma_get_asls();
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 0a08a15..5c9e15c 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -620,10 +620,6 @@
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -638,7 +634,7 @@
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
/* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
+ gnvs->aslb = intel_gma_get_asls();
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
--
To view, visit https://review.coreboot.org/19084
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib1c60a317ecfdd3189558b53018258eceb0f4955
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
More information about the coreboot-gerrit
mailing list