[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Cleanup code by using common FAST_SPI module
Barnali Sarkar (Code Review)
gerrit at coreboot.org
Mon Apr 3 15:18:49 CEST 2017
Barnali Sarkar has uploaded a new change for review. ( https://review.coreboot.org/19055 )
Change subject: soc/intel/skylake: Cleanup code by using common FAST_SPI module
......................................................................
soc/intel/skylake: Cleanup code by using common FAST_SPI module
This patch currently contains the following -
1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code.
2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library.
3. Use common FAST_SPI header file.
Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/bootblock/cpu.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/flash_controller.c
M src/soc/intel/skylake/include/soc/flash_controller.h
M src/soc/intel/skylake/include/soc/pch.h
D src/soc/intel/skylake/include/soc/spi.h
M src/soc/intel/skylake/pch.c
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/spi.c
M src/soc/intel/skylake/smihandler.c
12 files changed, 56 insertions(+), 281 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/19055/2
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 8ac7263..6c43725 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -50,6 +50,7 @@
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_LPSS_I2C
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index fab589f..040e847 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -14,20 +14,20 @@
* GNU General Public License for more details.
*/
-#include <stdint.h>
-#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/intel/microcode/microcode.c>
-#include <reset.h>
+#include <cpu/x86/mtrr.h>
+#include <delay.h>
+#include <intelblocks/fast_spi.h>
#include <lib.h>
+#include <reset.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/spi.h>
+#include <stdint.h>
/* Soft Reset Data Register Bit 12 = MAX Boot Frequency */
#define SPI_STRAP_MAX_FREQ (1<<12)
@@ -36,14 +36,7 @@
static void set_pch_cpu_strap(u8 flex_ratio)
{
- uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
- u32 ssl, ssms, soft_reset_data;
-
-
- /* Set Strap Lock Disable */
- ssl = read32(spibar + SPIBAR_RESET_LOCK);
- ssl |= SPIBAR_RESET_LOCK_DISABLE;
- write32(spibar + SPIBAR_RESET_LOCK, ssl);
+ u32 soft_reset_data;
/* Soft Reset Data Register Bit 12 = MAX Boot Frequency
* Bit 6-11 = Flex Ratio
@@ -51,17 +44,7 @@
*/
soft_reset_data = SPI_STRAP_MAX_FREQ;
soft_reset_data |= (flex_ratio << FLEX_RATIO_BIT);
- write32(spibar + SPIBAR_RESET_DATA, soft_reset_data);
-
- /* Set Strap Mux Select set to '1' */
- ssms = read32(spibar + SPIBAR_RESET_CTRL);
- ssms |= SPIBAR_RESET_CTRL_SSMC;
- write32(spibar + SPIBAR_RESET_CTRL, ssms);
-
- /* Set Strap Lock Enable */
- ssl = read32(spibar + SPIBAR_RESET_LOCK);
- ssl |= SPIBAR_RESET_LOCK_ENABLE;
- write32(spibar + SPIBAR_RESET_LOCK, ssl);
+ fast_spi_set_strap_msg_data(soft_reset_data);
}
static void set_flex_ratio_to_tdp_nominal(void)
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 60b22dc..61d02a2 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -18,6 +18,7 @@
#include <chip.h>
#include <device/device.h>
#include <device/pci_def.h>
+#include <intelblocks/fast_spi.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -31,38 +32,6 @@
/* Max PXRC registers in ITSS*/
#define MAX_PXRC_CONFIG 0x08
-
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(void)
-{
- u8 reg8 = pci_read_config8(PCH_DEV_SPI, 0xdc);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_write_config8(PCH_DEV_SPI, 0xdc, reg8);
-}
-
-static void enable_spibar(void)
-{
- device_t dev = PCH_DEV_SPI;
- u8 pcireg;
-
- /* Assign Resources to SPI Controller */
- /* Clear BIT 1-2 SPI Command Register */
- pcireg = pci_read_config8(dev, PCI_COMMAND);
- pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- pci_write_config8(dev, PCI_COMMAND, pcireg);
-
- /* Program Temporary BAR for SPI */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0,
- SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
-
- /* Enable Bus Master and MMIO Space */
- pcireg = pci_read_config8(dev, PCI_COMMAND);
- pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config8(dev, PCI_COMMAND, pcireg);
-}
static void enable_p2sbbar(void)
{
@@ -85,8 +54,7 @@
void bootblock_pch_early_init(void)
{
- enable_spibar();
- enable_spi_prefetch();
+ fast_spi_enable_bar(SPI_BASE_ADDRESS);
enable_p2sbbar();
}
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index e923dcd..f19ffce 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -20,9 +20,10 @@
#include <console/console.h>
#include <console/post_codes.h>
#include <cpu/x86/smm.h>
+#include <device/pci.h>
+#include <intelblocks/fast_spi.h>
#include <reg_script.h>
#include <spi-generic.h>
-#include <stdlib.h>
#include <soc/lpc.h>
#include <soc/me.h>
#include <soc/p2sb.h>
@@ -30,10 +31,8 @@
#include <soc/pcr.h>
#include <soc/pm.h>
#include <soc/smbus.h>
-#include <soc/spi.h>
#include <soc/systemagent.h>
-#include <device/pci.h>
-#include <chip.h>
+#include <stdlib.h>
static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
{
@@ -81,8 +80,7 @@
static void pch_finalize_script(void)
{
device_t dev;
- uint32_t reg32, hsfs;
- void *spibar = get_spi_bar();
+ uint32_t reg32;
u16 tcobase;
u16 tcocnt;
uint8_t *pmcbase;
@@ -90,15 +88,11 @@
u32 pmsyncreg;
u8 reg8;
- /* Set SPI opcode menu */
- write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX);
- write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE);
- write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER);
- write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER);
- /* Lock SPIBAR */
- hsfs = read32(spibar + SPIBAR_HSFS);
- hsfs |= SPIBAR_HSFS_FLOCKDN;
- write32(spibar + SPIBAR_HSFS, hsfs);
+ /* Set FAST_SPI opcode menu */
+ fast_spi_set_opcode_menu();
+
+ /* Lock FAST_SPIBAR */
+ fast_spi_lock_bar();
/*TCO Lock down */
tcobase = smbus_tco_regs();
@@ -164,12 +158,9 @@
BIOS_CNTL) | LPC_BC_BILD);
/* Reads back for posted write to take effect */
pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
- pci_write_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL,
- pci_read_config32(PCH_DEV_SPI,
- SPIBAR_BIOS_CNTL) |
- SPIBAR_BC_BILD);
- /* Reads back for posted write to take effect */
- pci_read_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL);
+
+ fast_spi_set_bios_interface_lock_down();
+
/* GCS reg of DMI */
pcr_andthenor8(PID_DMI, R_PCH_PCR_DMI_GCS, 0xFF,
B_PCH_PCR_DMI_GCS_BILD);
@@ -180,9 +171,8 @@
pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
pci_read_config8(PCH_DEV_LPC,
BIOS_CNTL) | LPC_BC_LE);
- pci_write_config8(PCH_DEV_SPI, BIOS_CNTL,
- pci_read_config8(PCH_DEV_SPI,
- BIOS_CNTL) | SPIBAR_BC_LE);
+
+ fast_spi_set_lock_enable();
}
/* SPIEiss */
@@ -190,10 +180,8 @@
pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
pci_read_config8(PCH_DEV_LPC,
BIOS_CNTL) | LPC_BC_EISS);
- pci_write_config8(PCH_DEV_SPI, BIOS_CNTL,
- pci_read_config8(PCH_DEV_SPI,
- SPIBAR_BIOS_CNTL) |
- SPIBAR_BC_EISS);
+
+ fast_spi_set_eiss();
}
}
diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index ac6758e..128039b 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -14,16 +14,17 @@
/* This file is derived from the flashrom project. */
#include <arch/early_variables.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
#include <bootstate.h>
-#include <timer.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/fast_spi_def.h>
#include <soc/flash_controller.h>
#include <soc/intel/common/spi_flash.h>
#include <soc/pci_devs.h>
-#include <soc/spi.h>
#include <spi-generic.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <timer.h>
static inline uint16_t spi_flash_read_hsfs(pch_spi_flash_regs * const regs)
{
@@ -98,7 +99,7 @@
int timeout_ms)
{
uint16_t hsfc;
- pch_spi_flash_regs * const regs = get_spi_bar();
+ pch_spi_flash_regs * const regs = fast_spi_get_bar();
/* Clear status prior to operation. */
spi_flash_clear_status(regs);
@@ -152,18 +153,6 @@
return size;
}
-void spi_flash_init(void)
-{
- uint8_t bios_cntl;
- device_t dev = PCH_DEV_SPI;
-
- /* Disable the BIOS write protect so write commands are allowed. */
- pci_read_config_byte(dev, SPIBAR_BIOS_CNTL, &bios_cntl);
- bios_cntl &= ~SPIBAR_BC_EISS;
- bios_cntl |= SPIBAR_BC_WPD;
- pci_write_config_byte(dev, SPIBAR_BIOS_CNTL, bios_cntl);
-}
-
int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len)
{
u32 start, end, erase_size;
@@ -201,7 +190,7 @@
pch_spi_flash_regs *spi_bar;
uint32_t temp32 = 0;
- spi_bar = get_spi_bar();
+ spi_bar = fast_spi_get_bar();
for (i = 0; i < len; i++) {
if ((i % 4) == 0)
@@ -216,7 +205,7 @@
{
uint8_t block_len;
- if (addr + len > spi_get_flash_size(get_spi_bar())) {
+ if (addr + len > spi_get_flash_size(fast_spi_get_bar())) {
printk(BIOS_ERR,
"Attempt to read %x-%x which is out of chip\n",
(unsigned int) addr,
@@ -254,7 +243,7 @@
int i;
pch_spi_flash_regs *spi_bar;
- spi_bar = get_spi_bar();
+ spi_bar = fast_spi_get_bar();
if (len <= 0)
return;
@@ -280,7 +269,7 @@
uint32_t start = addr;
pch_spi_flash_regs *spi_bar;
- spi_bar = get_spi_bar();
+ spi_bar = fast_spi_get_bar();
if (addr + len > spi_get_flash_size(spi_bar)) {
printk(BIOS_ERR,
@@ -333,7 +322,7 @@
flash = car_get_var_ptr(&boot_flash);
/* Ensure writes can take place to the flash. */
- spi_flash_init();
+ fast_spi_flash_init();
memcpy(&flash->spi, spi, sizeof(*spi));
flash->name = "Opaque HW-sequencing";
@@ -346,20 +335,20 @@
/* The hardware sequencing supports 4KiB or 64KiB erase. Use 4KiB. */
flash->sector_size = 4*KiB;
- flash->size = spi_get_flash_size(get_spi_bar());
+ flash->size = spi_get_flash_size(fast_spi_get_bar());
return flash;
}
int spi_flash_get_fpr_info(struct fpr_info *info)
{
- pch_spi_flash_regs *spi_bar = get_spi_bar();
+ pch_spi_flash_regs *spi_bar = fast_spi_get_bar();
if (!spi_bar)
return -1;
info->base = (uintptr_t)&spi_bar->pr[0];
- info->max = SPI_FPR_MAX;
+ info->max = SPIBAR_FPR_MAX;
return 0;
}
@@ -371,7 +360,7 @@
*/
static void spi_flash_init_cb(void *unused)
{
- spi_flash_init();
+ fast_spi_flash_init();
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index 712a18d..176649c 100644
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -28,8 +28,6 @@
void *buf);
int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg);
-void spi_flash_init(void);
-
#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{
diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h
index 9be75bf..48ecb85 100644
--- a/src/soc/intel/skylake/include/soc/pch.h
+++ b/src/soc/intel/skylake/include/soc/pch.h
@@ -35,7 +35,6 @@
u8 pch_revision(void);
u16 pch_type(void);
-u32 pch_read_soft_strap(int id);
void pch_log_state(void);
#if ENV_RAMSTAGE
void pch_disable_devfn(device_t dev);
diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h
deleted file mode 100644
index a92b78d..0000000
--- a/src/soc/intel/skylake/include/soc/spi.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_SPI_H_
-#define _SOC_SPI_H_
-
-/*
- * SPI Opcode Menu setup for SPIBAR lockdown
- * should support most common flash chips.
- */
-#define SPIDVID_OFFSET 0x0
-
-/* Reigsters within the SPIBAR */
-#define SPIBAR_SSFC 0xA1
-
-#define SPIBAR_PREOP 0xA4
-#define SPIBAR_OPTYPE 0xA6
-#define SPIBAR_OPMENU_LOWER 0xA8
-#define SPIBAR_OPMENU_UPPER 0xAc
-/* STRAP LOCK Register */
-#define SPIBAR_RESET_LOCK 0xF0
-#define SPIBAR_RESET_LOCK_DISABLE 0
-#define SPIBAR_RESET_LOCK_ENABLE 1
-/* STRAP MSG Control Register*/
-#define SPIBAR_RESET_CTRL 0xF4
-#define SPIBAR_RESET_CTRL_SSMC 1
-/* STRAP Data Register*/
-#define SPIBAR_RESET_DATA 0xF8
-
-#define SPI_FPR_MAX 5
-
-#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
-#define SPI_OPTYPE_0 0x01 /* Write, no address */
-
-#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
-#define SPI_OPTYPE_1 0x03 /* Write, address required */
-
-#define SPI_OPMENU_2 0x03 /* READ: Read Data */
-#define SPI_OPTYPE_2 0x02 /* Read, address required */
-
-#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
-#define SPI_OPTYPE_3 0x00 /* Read, no address */
-
-#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
-#define SPI_OPTYPE_4 0x03 /* Write, address required */
-
-#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
-#define SPI_OPTYPE_5 0x00 /* Read, no address */
-
-#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
-#define SPI_OPTYPE_6 0x03 /* Write, address required */
-
-#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
-#define SPI_OPTYPE_7 0x02 /* Read, address required */
-
-#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
- (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
-#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
- (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
-
-#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
- (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
- (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
- (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
-
-#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-
-#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
-#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
-#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
-#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
-#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
-#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
-#define SPIBAR_HSFS_BERASE_MASK 3 /* Block/Sector Erase MASK */
-#define SPIBAR_HSFS_BERASE_OFFSET 3 /* Block/Sector Erase OFFSET */
-#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
-#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
-#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
-#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
-#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
-#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
-#define SPIBAR_FADDR 0x08 /* SPI flash address */
-#define SPIBAR_FADDR_MASK 0x7FFFFFF
-
-#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
-#define SPIBAR_FPR(n) (0x84 + (4 * n)) /* SPI flash protected range */
-#define SPIBAR_FPR_WPE (1 << 31) /* Flash Write protected */
-#define SPIBAR_SSFS 0xA0
-#define SPIBAR_SSFS_ERROR (1 << 3)
-#define SPIBAR_SSFS_DONE (1 << 2)
-#define SPIBAR_SSFC 0xA1
-#define SPIBAR_SSFC_DATA (1 << 14)
-#define SPIBAR_SSFC_GO (1 << 1)
-
-#define SPIBAR_FDOC 0xB4
-#define SPIBAR_FDOC_COMPONENT (1 << 12)
-#define SPIBAR_FDOC_FDSI_1 (1 << 2)
-
-#define SPIBAR_FDOD 0xB8
-#define FLCOMP_C0DEN_MASK 0xF
-#define FLCOMP_C0DEN_8MB 4
-#define FLCOMP_C0DEN_16MB 5
-#define FLCOMP_C0DEN_32MB 6
-
-#define SPIBAR_BIOS_CNTL 0xDC
-#define SPIBAR_BC_BILD (1 << 7)
-#define SPIBAR_BC_EISS (1 << 5)
-#define SPIBAR_BC_LE (1 << 2)
-#define SPIBAR_BC_WPD (1 << 0)
-
-void *get_spi_bar(void);
-
-#endif
diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c
index ed64c8f..2bd4493 100644
--- a/src/soc/intel/skylake/pch.c
+++ b/src/soc/intel/skylake/pch.c
@@ -15,16 +15,16 @@
* GNU General Public License for more details.
*/
+#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
-#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
+#include <intelblocks/fast_spi.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
-#include <soc/spi.h>
u8 pch_revision(void)
{
@@ -34,34 +34,6 @@
u16 pch_type(void)
{
return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
-}
-
-void *get_spi_bar(void)
-{
- device_t dev = PCH_DEV_SPI;
- uint32_t bar;
-
- bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- /* Bits 31-12 are the base address as per EDS for SPI 1F/5,
- * Don't care about 0-11 bit
- */
- return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
-}
-
-u32 pch_read_soft_strap(int id)
-{
- uint32_t fdoc;
- void *spibar = get_spi_bar();
-
- fdoc = read32(spibar + SPIBAR_FDOC);
- fdoc &= ~0x00007ffc;
- write32(spibar + SPIBAR_FDOC, fdoc);
-
- fdoc |= 0x00004000;
- fdoc |= id * 4;
- write32(spibar + SPIBAR_FDOC, fdoc);
-
- return read32(spibar + SPIBAR_FDOD);
}
#if ENV_RAMSTAGE
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index fb261c3..063a8f8 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -14,8 +14,6 @@
* GNU General Public License for more details.
*/
-#include <stddef.h>
-#include <stdint.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/cbfs.h>
@@ -30,6 +28,7 @@
#include <device/pci.h>
#include <device/pci_def.h>
#include <elog.h>
+#include <intelblocks/fast_spi.h>
#include <reset.h>
#include <romstage_handoff.h>
#include <soc/pci_devs.h>
@@ -38,8 +37,9 @@
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/romstage.h>
-#include <soc/spi.h>
#include <stage_cache.h>
+#include <stddef.h>
+#include <stdint.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
index 41e06a7..0aab90b 100644
--- a/src/soc/intel/skylake/romstage/spi.c
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -14,9 +14,11 @@
* GNU General Public License for more details.
*/
+#include <intelblocks/fast_spi.h>
#include <soc/flash_controller.h>
#include <soc/romstage.h>
#include <spi-generic.h>
+#include <soc/pci_devs.h>
/*
* Minimal set of commands to read WPSR from SPI.
@@ -27,7 +29,7 @@
uint8_t rdsr;
int ret = 0;
- spi_flash_init();
+ fast_spi_flash_init();
/* sending NULL for spiflash struct parameter since we are not
* calling HWSEQ read_status() call via Probe.
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index 382bdfc..1e4defa 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -15,17 +15,17 @@
* GNU General Public License for more details.
*/
-#include <delay.h>
-#include <types.h>
#include <arch/hlt.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
-#include <device/pci_def.h>
#include <cpu/x86/smm.h>
-#include <spi-generic.h>
+#include <delay.h>
+#include <device/pci_def.h>
#include <elog.h>
+#include <intelblocks/fast_spi.h>
#include <pc80/mc146818rtc.h>
+#include <spi-generic.h>
#include <soc/flash_controller.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -36,6 +36,7 @@
#include <soc/pm.h>
#include <soc/pmc.h>
#include <soc/smm.h>
+#include <types.h>
static u8 smm_initialized = 0;
@@ -277,7 +278,7 @@
if (IS_ENABLED(CONFIG_SPI_FLASH_SMM))
/* Re-init SPI driver to handle locked BAR */
- spi_flash_init();
+ fast_spi_flash_init();
}
static void southbridge_smi_apmc(void)
--
To view, visit https://review.coreboot.org/19055
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
More information about the coreboot-gerrit
mailing list