[coreboot-gerrit] Change in coreboot[master]: cpu/intel/model_106cx: Add tsc_freq_mhz() function

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19067 )

Change subject: cpu/intel/model_106cx: Add tsc_freq_mhz() function
......................................................................

cpu/intel/model_106cx: Add tsc_freq_mhz() function

This adds a function to get TSC frequency which then gets stored in
coreboot tables. This allows to read timestamps on Intel Atom 230
using cbmem.

TESTED on d945gclf

Change-Id: Ifb6074f3f097d7e6fc501a376754a05eb9e4faa0
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_106cx/Makefile.inc
A src/cpu/intel/model_106cx/tsc_freq.c
2 files changed, 58 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/19067/1

diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc
index cd753db..9624c7c 100644
--- a/src/cpu/intel/model_106cx/Makefile.inc
+++ b/src/cpu/intel/model_106cx/Makefile.inc
@@ -1,5 +1,8 @@
 ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
+ramstage-y += tsc_freq.c
+romstage-y += tsc_freq.c
+smm-y      += tsc_freq.c
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
diff --git a/src/cpu/intel/model_106cx/tsc_freq.c b/src/cpu/intel/model_106cx/tsc_freq.c
new file mode 100644
index 0000000..9958369
--- /dev/null
+++ b/src/cpu/intel/model_106cx/tsc_freq.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/intel/speedstep.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+	msr_t msr;
+	unsigned long fsb = 0, divisor;
+
+	msr = rdmsr(MSR_FSB_FREQ);
+	switch (msr.lo & 0x07) {
+	case 5:
+		fsb = 400;
+		break;
+	case 1:
+		fsb = 533;
+		break;
+	case 3:
+		fsb = 667;
+		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
+	}
+
+	msr = rdmsr(IA32_PERF_STS);
+	divisor = (msr.hi >> 8) & 0x1f;
+
+	return (fsb * divisor) / 4;
+}

-- 
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifb6074f3f097d7e6fc501a376754a05eb9e4faa0
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>