[coreboot-gerrit] New patch to review for coreboot: fsp_Broadwell_DE: Set proper UART register width
Kevin Herbert (kevin@trippers.org)
gerrit at coreboot.org
Mon Sep 26 23:40:03 CEST 2016
Kevin Herbert (kevin at trippers.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16748
-gerrit
commit 0270cdb826db2481b3d5352373bb0220cb1ae345
Author: Kevin Paul Herbert <kevin at trippers.org>
Date: Mon Sep 26 14:23:43 2016 -0700
fsp_Broadwell_DE: Set proper UART register width
The FSP version of Broadwell UART support removes the UART hardware
initialization, as the FSP initializes the UART. Too much of
the software initialization was removed, as the setup of the register
width was omitted. This impacts payloads using coreboot tables for
UART configuration, such as libpayload.
Reproduced using FILO on Intel Camelback Mountain CRB.
Change-Id: Iac43a5f8128eaa5c958649cf07d97e8623fb8ac3
---
src/soc/intel/fsp_broadwell_de/uart.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/fsp_broadwell_de/uart.c b/src/soc/intel/fsp_broadwell_de/uart.c
index d22dd0d..e1e1acd 100644
--- a/src/soc/intel/fsp_broadwell_de/uart.c
+++ b/src/soc/intel/fsp_broadwell_de/uart.c
@@ -105,6 +105,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_IO_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);
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