[coreboot-gerrit] Patch set updated for coreboot: mainboards/google/reef: use chromeec's ASL lid switch implementation
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Sat Sep 24 04:26:29 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16733
-gerrit
commit df896c50b9f783a98f8002d315ae30b3d535bc46
Author: Aaron Durbin <adurbin at chromium.org>
Date: Fri Sep 23 16:08:21 2016 -0500
mainboards/google/reef: use chromeec's ASL lid switch implementation
Defer to the lid switch implementation provided by the chromeec.
BUG=chrome-os-partner:56677
Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/reef/dsdt.asl | 14 --------------
.../google/reef/variants/baseboard/include/baseboard/ec.h | 5 +++++
2 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index bfdd765..dc63436 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -46,20 +46,6 @@ DefinitionBlock(
/* Chipset specific sleep states */
#include <soc/intel/apollolake/acpi/sleepstates.asl>
- /* LID */
- Scope (\_SB)
- {
- Device (LID0)
- {
- Name (_HID, EisaId ("PNP0C0D"))
- Method (_LID, 0)
- {
- Return (\_SB.PCI0.LPCB.EC0.LIDS)
- }
- Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
- }
- }
-
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
index f2be328..87c127c 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
@@ -16,6 +16,7 @@
#ifndef BASEBOARD_EC_H
#define BASEBOARD_EC_H
+#include <variant/gpio.h>
#include <ec/google/chromeec/ec_commands.h>
#define MAINBOARD_EC_SCI_EVENTS \
@@ -64,6 +65,10 @@
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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