[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: provide power button ACPI device

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16731

-gerrit

commit 9a85618970c162cf4968bfc86cd9da567b4c9ebd
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 23 15:06:37 2016 -0500

    soc/intel/apollolake: provide power button ACPI device
    
    Instead of having each mainboard provide the power button,
    uncondtionally provide the power button ACPI device on behalf
    of each mainboard.
    
    BUG=chrome-os-partner:56677
    
    Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/reef/dsdt.asl            | 7 +------
 src/soc/intel/apollolake/acpi/southbridge.asl | 9 +++++++++
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index 3265941..bfdd765 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -46,7 +46,7 @@ DefinitionBlock(
 	/* Chipset specific sleep states */
 	#include <soc/intel/apollolake/acpi/sleepstates.asl>
 
-	/* LID and Power button. */
+	/* LID  */
 	Scope (\_SB)
 	{
 		Device (LID0)
@@ -58,11 +58,6 @@ DefinitionBlock(
 			}
 			Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
 		}
-
-		Device (PWRB)
-		{
-			Name (_HID, EisaId ("PNP0C0C"))
-		}
 	}
 
 	/* Chrome OS Embedded Controller */
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..1c10f1a 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -17,6 +17,15 @@
 
 #include <soc/gpe.h>
 
+/* Power button. */
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+	}
+}
+
 /* PCIE device */
 #include "pcie.asl"