[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support
Lijian Zhao (lijian.zhao@intel.com)
gerrit at coreboot.org
Tue Sep 20 22:34:07 CEST 2016
Lijian Zhao (lijian.zhao at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649
-gerrit
commit ffd1f8720dcca4df50c543a36341ef4a0751f4fe
Author: Zhao, Lijian <lijian.zhao at intel.com>
Date: Tue Sep 6 18:48:19 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The
ACPI mode entry include resources for PMC_IPC, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successully and check with dmesg to see the
driver had been loadded success without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao at intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 58 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++
2 files changed, 61 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..2dc5323
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+ Name (_ADR, 0x0) //ACPI MODE as P2SB got hidden in OS
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MDAT)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MINF)
+ IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH,
+ 0x04, PMIO_LENGTH)
+ Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store (PMC_BAR0, IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store (MCH_BASE_ADDR+MAILBOX_DATA, MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store (MCH_BASE_ADDR+MAILBOX_INTF, MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store (PMC_SRAM_BASE_0, SBAS)
+
+ Return (^RBUF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..11c27ea 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,6 +31,9 @@
#include "xhci.asl"
+/* PMC IPC */
+#include "pmc_ipc.asl"
+
/* LPC */
#include "lpc.asl"
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