[coreboot-gerrit] Patch merged into coreboot/master: rockchip: spi: Improve SPI read efficiency

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 03cd118025e0f7aab139254e07f9d1dca3c242e5
Author: Simon Glass <sjg at chromium.org>
Date:   Sat Aug 27 15:10:30 2016 -0600

    rockchip: spi: Improve SPI read efficiency
    
    The SPI driver is quite slow at reading data. For example, with a 24MHz
    clock on gru it achieves a read speed of only 13.9Mbps.
    
    We can correct this by reading the status registers once, then reading as
    many bytes as are available before checking the status registers again. It
    seems likely that a status register read requires synchronizing with the
    SPI FIFO clock domain, which takes a while.
    
    BUG=chrome-os-partner:56556
    BRANCH=none
    TEST=run on gru and see the speed increase from 13.920 Mbps to 24.712 Mbps
    
    Change-Id: I24aed0c9c6c5445634c4e056922afaee4e9a7b33
    Signed-off-by: Martin Roth <martinroth at chromium.org>
    Original-Commit-Id: 49c2fc20d7d7d703763e9b0a6f68313a349a84b9
    Original-Change-Id: I42745f01f0fe069f6ae26d866004d36bb257e6b2
    Original-Signed-off-by: Simon Glass <sjg at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/376945
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: https://review.coreboot.org/16582
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See https://review.coreboot.org/16582 for details.

-gerrit