[coreboot-gerrit] New patch to review for coreboot: Added basic Skylake Saddle Brook board support
Boon Tiong Teo (boon.tiong.teo@intel.com)
gerrit at coreboot.org
Thu Sep 15 06:38:23 CEST 2016
Boon Tiong Teo (boon.tiong.teo at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16608
-gerrit
commit 47a8f6d9b5928adce318533fbc9a1122ae57d5e3
Author: Teo Boon Tiong <boon.tiong.teo at intel.com>
Date: Thu Sep 15 11:49:04 2016 +0800
Added basic Skylake Saddle Brook board support
Change-Id: I95c752922a74369cb8ae77be6cb886e4597814e4
Signed-off-by: Teo Boon Tiong <boon.tiong.teo at intel.com>
---
src/mainboard/intel/sklsdlbrk/Kconfig | 45 ++++++++
src/mainboard/intel/sklsdlbrk/Kconfig.name | 2 +
src/mainboard/intel/sklsdlbrk/acpi/ec.asl | 14 +++
src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl | 26 +++++
src/mainboard/intel/sklsdlbrk/acpi/superio.asl | 14 +++
src/mainboard/intel/sklsdlbrk/acpi_tables.c | 15 +++
src/mainboard/intel/sklsdlbrk/cmos.layout | 135 +++++++++++++++++++++++
src/mainboard/intel/sklsdlbrk/devicetree.cb | 112 +++++++++++++++++++
src/mainboard/intel/sklsdlbrk/dsdt.asl | 49 ++++++++
src/mainboard/intel/sklsdlbrk/fadt.c | 47 ++++++++
src/mainboard/intel/sklsdlbrk/onboard.h | 37 +++++++
src/mainboard/intel/sklsdlbrk/romstage.c | 90 +++++++++++++++
src/mainboard/intel/sklsdlbrk/spd/Makefile.inc | 17 +++
src/mainboard/intel/sklsdlbrk/spd/empty.spd.hex | 16 +++
src/mainboard/intel/sklsdlbrk/spd/spd.c | 125 +++++++++++++++++++++
src/mainboard/intel/sklsdlbrk/spd/spd.h | 41 +++++++
16 files changed, 785 insertions(+)
diff --git a/src/mainboard/intel/sklsdlbrk/Kconfig b/src/mainboard/intel/sklsdlbrk/Kconfig
new file mode 100644
index 0000000..656d165
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/Kconfig
@@ -0,0 +1,45 @@
+if BOARD_INTEL_SKLSDLBRK
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_SMI_HANDLER
+ select MMCONF_SUPPORT
+ select MONOTONIC_TIMER_MSR
+ select PCIEXP_L1_SUB_STATE
+ select SOC_INTEL_SKYLAKE
+ select SKYLAKE_SOC_PCH_H
+ select SUPERIO_NUVOTON_NCT6776
+ select SUPERIO_NUVOTON_NCT6776_COM_A
+ select CONSOLE_SERIAL
+ select DRIVERS_UART
+
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config BOOT_MEDIA_SPI_BUS
+ int
+ default 0
+
+config MAINBOARD_DIR
+ string
+ default "intel/sklsdlbrk"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Skylake Saddle Brook"
+
+config MAX_CPUS
+ int
+ default 8
+
+config VBOOT_RAMSTAGE_INDEX
+ hex
+ default 0x3
+
+endif
diff --git a/src/mainboard/intel/sklsdlbrk/Kconfig.name b/src/mainboard/intel/sklsdlbrk/Kconfig.name
new file mode 100644
index 0000000..c85fb81
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_SKLSDLBRK
+ bool "Skylake Saddle Brook"
diff --git a/src/mainboard/intel/sklsdlbrk/acpi/ec.asl b/src/mainboard/intel/sklsdlbrk/acpi/ec.asl
new file mode 100644
index 0000000..de9dc8c
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/acpi/ec.asl
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl b/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl
new file mode 100644
index 0000000..ddccc21
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/acpi/mainboard.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpio.h>
+#include <mainboard/intel/sklsdlbrk/onboard.h>
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
\ No newline at end of file
diff --git a/src/mainboard/intel/sklsdlbrk/acpi/superio.asl b/src/mainboard/intel/sklsdlbrk/acpi/superio.asl
new file mode 100644
index 0000000..de9dc8c
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/acpi/superio.asl
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/intel/sklsdlbrk/acpi_tables.c b/src/mainboard/intel/sklsdlbrk/acpi_tables.c
new file mode 100644
index 0000000..ccf9f74
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/acpi_tables.c
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/intel/sklsdlbrk/cmos.layout b/src/mainboard/intel/sklsdlbrk/cmos.layout
new file mode 100644
index 0000000..8467747
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/cmos.layout
@@ -0,0 +1,135 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2015 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/intel/sklsdlbrk/devicetree.cb b/src/mainboard/intel/sklsdlbrk/devicetree.cb
new file mode 100644
index 0000000..bd2a552
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/devicetree.cb
@@ -0,0 +1,112 @@
+chip soc/intel/skylake
+
+ # SerialIO device modes
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C3] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoPci, \
+ [PchSerialIoIndexSpi0] = PchSerialIoPci, \
+ [PchSerialIoIndexSpi1] = PchSerialIoPci, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoPci, \
+ }"
+
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0a"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x0b"
+ register "pirqf_routing" = "0x0b"
+ register "pirqg_routing" = "0x0b"
+ register "pirqh_routing" = "0x0b"
+
+ # Enable S0ix
+ register "s0ix_enable" = "0"
+
+ # Probeless Trace function
+ register "ProbelessTrace" = "0"
+
+ # I/O Buffer Ownership:
+ # 0: HD-A Link
+ # 1 Shared, HD-A Link and I2S Port
+ # 3: I2S Ports
+ register "IoBufferOwnership" = "3"
+
+ # Audio related
+ register "DspEnable" = "0"
+
+ # USB related
+ register "SsicPortEnable" = "0"
+
+ # eMMC
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "2"
+
+ # Integrated Sensor
+ register "IshEnable" = "0"
+
+ # XDCI controller
+ register "XdciEnable" = "0"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT-Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 on end # I2C #5
+ device pci 19.2 on end # I2C #4
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express Port 13
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1b.0 off end # PCI Express Port 17
+ device pci 1b.1 off end # PCI Express Port 18
+ device pci 1b.2 off end # PCI Express Port 19
+ device pci 1b.3 off end # PCI Express Port 20
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 on end # UART #1
+ device pci 1e.2 on end # GSPI #0
+ device pci 1e.3 on end # GSPI #1
+ device pci 1e.4 off end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 on end # SDCard
+ device pci 1f.0 on end # LPC Interface (eSPI Enable Strap = 0) eSPI Interface (eSPI Enable Strap = 1)
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus Controller
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 on end # GbE
+ end
+end
diff --git a/src/mainboard/intel/sklsdlbrk/dsdt.asl b/src/mainboard/intel/sklsdlbrk/dsdt.asl
new file mode 100644
index 0000000..4134867
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/dsdt.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <soc/intel/skylake/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+ }
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/intel/sklsdlbrk/fadt.c b/src/mainboard/intel/sklsdlbrk/fadt.c
new file mode 100644
index 0000000..05fea01
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/fadt.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 5;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum = acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/intel/sklsdlbrk/onboard.h b/src/mainboard/intel/sklsdlbrk/onboard.h
new file mode 100644
index 0000000..b6c77e7
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/onboard.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+/*
+ * Gpio based irq for touchpad, 18th index in North Bank
+ * MAX_DIRECT_IRQ + GPSW_SIZE + 19
+ */
+#define SKLSDLBRK_TOUCHPAD_IRQ 33
+
+#define SKLRVPSDLBRK_TOUCH_IRQ 31
+
+#define BOARD_TOUCHPAD_NAME "touchpad"
+#define BOARD_TOUCHPAD_IRQ SKLSDLBRK_TOUCHPAD_IRQ
+#define BOARD_TOUCHPAD_I2C_BUS 0
+#define BOARD_TOUCHPAD_I2C_ADDR 0x20
+
+#define BOARD_TOUCHSCREEN_NAME "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ SKLRVPSDLBRK_TOUCH_IRQ
+#define BOARD_TOUCHSCREEN_I2C_BUS 0
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c
+
+#endif
diff --git a/src/mainboard/intel/sklsdlbrk/romstage.c b/src/mainboard/intel/sklsdlbrk/romstage.c
new file mode 100644
index 0000000..b4bc0c8
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/romstage.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/cpu.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include "spd/spd.h"
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+
+void car_mainboard_pre_console_init(void)
+{
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_romstage_entry(struct romstage_params *params)
+{
+ post_code(0x31);
+ /* Fill out PEI DATA */
+ mainboard_fill_pei_data(params->pei_data);
+ mainboard_fill_spd_data(params->pei_data);
+ /* Initliaze memory */
+ romstage_common(params);
+}
+
+void mainboard_memory_init_params(
+ struct romstage_params *params,
+ MEMORY_INIT_UPD *mupd)
+{
+ /* Get SPD data passing strucutre and initialize it.*/
+ if (params->pei_data->spd_data[0][0][0] != 0) {
+ mupd->MemorySpdPtr00 =
+ (UINT32)(params->pei_data->spd_data[0][0]);
+ mupd->MemorySpdPtr10 =
+ (UINT32)(params->pei_data->spd_data[1][0]);
+ }
+ printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
+ mupd->MemorySpdPtr00);
+ printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n",
+ mupd->MemorySpdPtr01);
+ printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
+ mupd->MemorySpdPtr10);
+ printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n",
+ mupd->MemorySpdPtr11);
+
+ /*
+ * Configure the DQ/DQS settings if required. In general the settings
+ * should be set in the FSP flash image and should not need to be
+ * changed.
+ */
+ memcpy(mupd->DqByteMapCh0, params->pei_data->dq_map[0],
+ sizeof(params->pei_data->dq_map[0]));
+ memcpy(mupd->DqByteMapCh1, params->pei_data->dq_map[1],
+ sizeof(params->pei_data->dq_map[1]));
+ memcpy(mupd->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
+ sizeof(params->pei_data->dqs_map[0]));
+ memcpy(mupd->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
+ sizeof(params->pei_data->dqs_map[1]));
+ memcpy(mupd->RcompResistor, params->pei_data->RcompResistor,
+ sizeof(params->pei_data->RcompResistor));
+ memcpy(mupd->RcompTarget, params->pei_data->RcompTarget,
+ sizeof(params->pei_data->RcompTarget));
+
+ /* update spd length*/
+ mupd->MemorySpdDataLen = SPD_LEN;
+ mupd->DqPinsInterleaved = TRUE;
+}
diff --git a/src/mainboard/intel/sklsdlbrk/spd/Makefile.inc b/src/mainboard/intel/sklsdlbrk/spd/Makefile.inc
new file mode 100644
index 0000000..8d2362e
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/spd/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd.c
diff --git a/src/mainboard/intel/sklsdlbrk/spd/empty.spd.hex b/src/mainboard/intel/sklsdlbrk/spd/empty.spd.hex
new file mode 100644
index 0000000..9ec39f1
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/sklsdlbrk/spd/spd.c b/src/mainboard/intel/sklsdlbrk/spd/spd.c
new file mode 100644
index 0000000..97b46b1
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/spd/spd.c
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <lib.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <soc/smbus.h>
+#include <soc/iomap.h>
+#include "spd.h"
+
+/* smbus read byte */
+int smbus_rb(unsigned int device, unsigned int address)
+{
+ return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
+}
+
+/* smbus write byte */
+int smbus_wb(unsigned int device, unsigned int address, unsigned int value)
+{
+ return do_smbus_write_byte(SMBUS_BASE_ADDRESS, device, address, value);
+}
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 4, 8, -1, -1, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, 17, 18, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 3];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 0xf] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ case SPD_DRAM_DDR4:
+ printk(BIOS_INFO, "DDR4\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO,
+ "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
+ banks, ranks, rows, cols, capmb);
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ int ch;
+ int dimm;
+ int i;
+ uint8_t saddr; //smbus slave address
+
+ /* Read SPD data via SMBus */
+ for (ch = 0; ch < 2; ch++) {
+ for (dimm = 0; dimm < 2; dimm++) {
+ saddr =
+ pei_data->spd_addresses[ch * 2 + dimm] >> 1;
+
+ smbus_wb(SPD_PAGE_ADDRESS_0 >> 1, 0, 0);
+ for (i = 0; i < SPD_LEN / 2; i++)
+ pei_data->spd_data[ch][dimm][i] =
+ smbus_rb(saddr, i);
+
+ smbus_wb(SPD_PAGE_ADDRESS_1 >> 1, 0, 0);
+
+ for (i = 256; i < SPD_LEN; i++)
+ pei_data->spd_data[ch][dimm][i] =
+ smbus_rb(saddr, i);
+
+ mainboard_print_spd_info(pei_data->spd_data[ch][dimm]);
+
+ hexdump(pei_data->spd_data[ch][dimm], SPD_LEN);
+ }
+ }
+}
diff --git a/src/mainboard/intel/sklsdlbrk/spd/spd.h b/src/mainboard/intel/sklsdlbrk/spd/spd.h
new file mode 100644
index 0000000..c9d5e08
--- /dev/null
+++ b/src/mainboard/intel/sklsdlbrk/spd/spd.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MAINBOARD_SPD_H_
+#define _MAINBOARD_SPD_H_
+
+#define SPD_LEN 512 // DDR4 SPD data length
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DRAM_DDR4 0x0c
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 12
+#define SPD_BUS_DEV_WIDTH 13
+#define SPD_PART_OFF 329 // DDR4 part number offset
+#define SPD_PART_LEN 19
+
+#define SPD_PAGE_ADDRESS_0 0x6c
+#define SPD_PAGE_ADDRESS_1 0x6e
+
+/* smbus read byte */
+int smbus_rb(unsigned int device, unsigned int address);
+/* smbus write byte */
+int smbus_wb(unsigned int device, unsigned int address, unsigned int value);
+
+#endif /* _MAINBOARD_SPD_H_ */
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