[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: initialize GNVS structure to 0

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 9e81540b85c6d06c7c3c63447b92f09590f032d1
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Sep 13 12:31:57 2016 -0500

    soc/intel/apollolake: initialize GNVS structure to 0
    
    The code was not previously initializing the GNVS structure
    to all 0's in the ACPI write tables path. Fix this and also
    rearrange the ordering of updating the fields to only handle
    the chip_info specific bits till last such that most of the
    structure is filled in prior to bailing out in the case of a
    bad devicetree.
    
    Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/16597
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-by: Furquan Shaikh <furquan at google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>
    Reviewed-by: Shaunak Saha <shaunak.saha at intel.com>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/16597 for details.

-gerrit