[coreboot-gerrit] New patch to review for coreboot: intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16565

-gerrit

commit 02909c98ed2127e964d0eca98003c58d70fa24a4
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri Sep 9 14:50:34 2016 -0700

    intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit
    
    This patch removes setting of gpio_tier1_sci_en from mainboard
    smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
    now.
    
    BUG=chrome-os-partner:56483
    TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
         Also from S0iX system is resuming for WIFI wake.
    
    Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/mainboard/intel/amenia/smihandler.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mainboard/intel/amenia/smihandler.c b/src/mainboard/intel/amenia/smihandler.c
index 05d363f..eb5377b 100644
--- a/src/mainboard/intel/amenia/smihandler.c
+++ b/src/mainboard/intel/amenia/smihandler.c
@@ -22,9 +22,6 @@
 
 void mainboard_smi_sleep(u8 slp_typ)
 {
-	if (slp_typ == ACPI_S3)
-		enable_gpe(GPIO_TIER_1_SCI);
-
 	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
 		chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
 					MAINBOARD_EC_S5_WAKE_EVENTS);