[coreboot-gerrit] New patch to review for coreboot: soc/apollolake: Set up GPIO_TIER1_SCI_EN properly

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16564

-gerrit

commit 63b39cac8364d442d4e286e1397b967186fc8020
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri Sep 9 11:43:03 2016 -0700

    soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
    
    Currently we are setting the gpio_tier1_sci in smihandler before
    going to S3. But this won't work for S0iX as it happens from Linux
    kernel and SMI handler is not involved in that flow. We need to
    set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
    kernel before going to sleep checks what values are passed through
    ASL as wake events(through _PRW), keeps those enabled only and
    clears other bits in gpe0 enable registers. So we need to inform
    the kernel to keep gpio_tier_sci also set as these are needed for
    any wake. This patch adds a _PRW method to powerbutton asl code.
    We can use the _PRW method of powerbutton. The reason of choosing
    powerbutton is its the default wake source and does not need any
    _PRW method defined and we cannot define more than one _PRW for
    any other wake source.
    
    BUG=chrome-os-partner:56483
    TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
         Also from S0iX system is resuming for WIFI wake.
    
    Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/soc/intel/apollolake/acpi/gpio.asl           | 5 +++++
 src/soc/intel/apollolake/include/soc/gpio_defs.h | 6 ++++++
 src/soc/intel/apollolake/include/soc/pm.h        | 6 ------
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index 03b8edd..ccf915e 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -141,6 +141,11 @@ scope (\_SB) {
 			Return(0xf)
 		}
 	}
+	Device (SLP)
+	{
+		Name (_HID, EisaId ("PNP0C0E"))
+		Name (_PRW, Package() { GPIO_TIER_1_SCI, 0x3 })
+	}
 }
 
 Scope(\_GPE)
diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h
index 70f86ca..6a7f21a 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_defs.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h
@@ -40,6 +40,12 @@
 
 #define GPIO_MAX_NUM_PER_GROUP	32
 
+/*
+ * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
+ * and/or an SCI or SMI#.
+ */
+#define GPIO_TIER_1_SCI		15
+
 #define MISCCFG_GPE0_DW0_SHIFT 8
 #define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
 #define MISCCFG_GPE0_DW1_SHIFT 12
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 3ee7403..2c12c8d 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -138,12 +138,6 @@
 #define   PCIE_GPE_EN		(1 << 9)
 #define   SWGPE_EN		(1 << 2)
 
-/*
- * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
- * and/or an SCI or SMI#.
- */
-#define GPIO_TIER_1_SCI		(1 << 15)
-
 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
 #define PRSTS			0x1000
 #define GEN_PMCON1		0x1020