[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Configure DW0 and DW1 GPIO registers through ASL

[Vaibhav Shankar (vaibhav.shankar@intel.com)]

Vaibhav Shankar (vaibhav.shankar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16349

-gerrit

commit 214a542ea3c4f2b1c3e7bde2a1764e61c356995b
Author: Vaibhav Shankar <vaibhav.shankar at intel.com>
Date:   Mon Aug 29 14:03:38 2016 -0700

    soc/intel/apollolake: Configure DW0 and DW1 GPIO registers through ASL
    
    Implemented an Iosf function to calculate DW0 register
    address. GPIO ASL methods can be used to configure GPIOs
    through ASL code. Added a variable to store PERST_0 GPIO.
    
    BUG=chrome-os-partner:55877
    
    Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e
    Signed-off-by: Vaibhav Shankar <vaibhav.shankar at intel.com>
---
 src/soc/intel/apollolake/acpi/gpiolib.asl   | 73 +++++++++++++++++++++++++++++
 src/soc/intel/apollolake/chip.h             |  3 ++
 src/soc/intel/apollolake/gpio.c             | 10 ++++
 src/soc/intel/apollolake/include/soc/gpio.h |  2 +
 src/soc/intel/apollolake/include/soc/iosf.h |  4 ++
 5 files changed, 92 insertions(+)

diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl
new file mode 100644
index 0000000..e3da4e8
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/gpiolib.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+
+	/* Get Pad Configuration DW0 register value */
+	Method (GPC0, 0x1, Serialized)
+	{
+		/* Arg0 - GPIO DW0 address */
+		Store (Arg0, Local0)
+		OperationRegion (PDW0, SystemMemory,
+			 Local0, 4)
+		Field (PDW0, AnyAcc, NoLock, Preserve) {
+			TEMP, 32
+		}
+		Return (TEMP)
+	}
+
+	/* Set Pad Configuration DW0 register value */
+	Method (SPC0, 0x2, Serialized)
+	{
+		/* Arg0 - GPIO DW0 address */
+		/* Arg1 - Value for DW0 register */
+		Store (Arg0, Local0)
+		OperationRegion (PDW0, SystemMemory,
+			 Local0, 4)
+		Field (PDW0, AnyAcc, NoLock, Preserve) {
+			TEMP,32
+		}
+		Store (Arg1, TEMP)
+	}
+
+	/* Get Pad Configuration DW1 register value */
+	Method (GPC1, 0x1, Serialized)
+	{
+		/* Arg0 - GPIO DW0 address */
+		Store (Add (Arg0, 0x4), Local0)
+		OperationRegion (PDW1, SystemMemory,
+			 Local0, 4)
+		Field (PDW1, AnyAcc, NoLock, Preserve) {
+			TEMP, 32
+		}
+		Return (TEMP)
+	}
+
+
+	/* Set Pad Configuration DW1 register value */
+	Method (SPC1, 0x2, Serialized)
+	{
+		/* Arg0 - GPIO DW0 address */
+		/* Arg1 - Value for DW1 register */
+		Store (Add (Arg0, 0x4), Local0)
+		OperationRegion (PDW1, SystemMemory,
+			Local0, 4)
+		Field(PDW1, AnyAcc, NoLock, Preserve) {
+			TEMP,32
+		}
+		Store (Arg1, TEMP)
+	}
+}
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 22217a4..bfd4364 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -109,6 +109,9 @@ struct soc_intel_apollolake_config {
 
 	/* SLP S3 minimum assertion width. */
 	int slp_s3_assertion_width_usecs;
+
+	/* GPIO pin for PERST_0 */
+	uint16_t prt0_gpio;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c
index e56f147..9288b10 100644
--- a/src/soc/intel/apollolake/gpio.c
+++ b/src/soc/intel/apollolake/gpio.c
@@ -177,6 +177,16 @@ void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
 		gpio_configure_pad(cfg + i);
 }
 
+void* gpio_dwx_address(const uint16_t pad)
+{
+	/* Calculate Address of DW0 register for given GPIO
+	 * pad - GPIO number
+	 * returns - address of GPIO
+	 */
+	const struct pad_community *comm = gpio_get_community(pad);
+	return iosf_address(comm->port, PAD_CFG_OFFSET(pad - comm->first_pad));
+}
+
 void gpio_input_pulldown(gpio_t gpio)
 {
 	struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP);
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 0089444..f7ef108 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -160,6 +160,8 @@ struct pad_config {
 void gpio_configure_pad(const struct pad_config *cfg);
 void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
 
+/* Calculate GPIO DW0 address */
+void* gpio_dwx_address(const uint16_t pad);
 /*
  * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
  * are passed which is then mapped to proper groups for MISCCFG. This basically
diff --git a/src/soc/intel/apollolake/include/soc/iosf.h b/src/soc/intel/apollolake/include/soc/iosf.h
index ae3e8ec..5b960de 100644
--- a/src/soc/intel/apollolake/include/soc/iosf.h
+++ b/src/soc/intel/apollolake/include/soc/iosf.h
@@ -36,4 +36,8 @@ inline static uint32_t iosf_read(uint16_t port, uint16_t reg)
 	return read32((void *)base);
 }
 
+static inline void* iosf_address(uint16_t port, uint16_t reg)
+{
+	return (void *) (CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3));
+}
 #endif /* _SOC_APOLLOLAKE_IOSF_H_ */