[coreboot-gerrit] Patch merged into coreboot/master: drivers/i2c/tpm: Add support for cr50 TPM

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit ffa765f6eb49d242df6c74f63c4aa1e6f65143e3
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 1 15:50:22 2016 -0700

    drivers/i2c/tpm: Add support for cr50 TPM
    
    Add support for the cr50 TPM used in apollolake chromebooks.
    This requires custom handling due to chip limitations, which
    may be revisited but are needed to get things working today.
    
    - timeouts need to be longer
    - must use the older style write+wait+read read protocol
    - all 4 bytes of status register must be read at once
    - same limitation applies when reading burst count from status reg
    - burst count max is 63 bytes, and burst count behaves
    slightly differently than other I2C TPMs
    - TPM expects the host to drain the full burst count (63 bytes)
    from the FIFO on a read
    
    Luckily the existing driver provides most abstraction needed to
    make this work seamlessly.  To maximize code re-use the support
    for cr50 is added directly instead of as a separate driver and the
    style is kept similar to the rest of the driver code.
    
    This was tested with the cr50 TPM on a reef board with vboot
    use of TPM for secdata storage and factory initialization.
    
    Change-Id: I9b0bc282e41e779da8bf9184be0a11649735a101
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/16396
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Philipp Deppenwiese <zaolin.daisuki at googlemail.com>


See https://review.coreboot.org/16396 for details.

-gerrit