[coreboot-gerrit] Patch merged into coreboot/master: fsp_baytrail: Refactor code for SPI debug messages

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit bd366ab4852adcb3734087af952e9b361e5c8bf9
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Mon Sep 5 07:40:29 2016 +0200

    fsp_baytrail: Refactor code for SPI debug messages
    
    Use the config switch CONFIG_DEBUG_SPI_FLASH on compiler level rather
    then on preprocessor level to ensure that the code is compiled even if
    the switch is not selected. In addition the following two changes are
    introduced:
    
    1. Prepend the debug messages with 'SPI:' to make the output more
       meaningful.
    2. Change the address mask from 0xffff to 0x3ff and remove the subtraction
       of the constant value 0xf020 in order to print only the register
       offset within the SPI controller and avoid the visibility of any
       fragments from SPI base address.
    3. Switch to uint8_t and friends instead of u8 to sync up with other
       code in the same file.
    
    Change-Id: Iaf46f29a775039007a402fe862839df06a4cbfaa
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
    Reviewed-on: https://review.coreboot.org/16499
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/16499 for details.

-gerrit