[coreboot-gerrit] New patch to review for coreboot: southbridge/amd/rs780: transition away from device_t
Antonello Dettori (dev@dettori.io)
gerrit at coreboot.org
Sat Sep 3 11:42:51 CEST 2016
Antonello Dettori (dev at dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16477
-gerrit
commit 8d815dc37888fa504c9a68a2c43ea0658c52882f
Author: Antonello Dettori <dev at dettori.io>
Date: Sat Sep 3 10:45:33 2016 +0200
southbridge/amd/rs780: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/rs780.
Change-Id: Ia9929baeec7423e9e2f06324038ddfbec006beb7
Signed-off-by: Antonello Dettori <dev at dettori.io>
---
src/southbridge/amd/rs780/early_setup.c | 50 ++++++++++++++++-----------------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index c61493d..b0a40be 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -19,49 +19,49 @@
#define NBMISC_INDEX 0x60
#define NBMC_INDEX 0xE8
-static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
+static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
{
pci_write_config32(dev, index_reg, index);
return pci_read_config32(dev, index_reg + 0x4);
}
-static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
+static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data)
{
pci_write_config32(dev, index_reg, index /* | 0x80 */ );
pci_write_config32(dev, index_reg + 0x4, data);
}
-static u32 nbmisc_read_index(device_t nb_dev, u32 index)
+static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
}
-static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
+static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
}
-static u32 htiu_read_index(device_t nb_dev, u32 index)
+static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
}
-static void htiu_write_index(device_t nb_dev, u32 index, u32 data)
+static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
}
-static u32 nbmc_read_index(device_t nb_dev, u32 index)
+static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
{
return nb_read_index((nb_dev), NBMC_INDEX, (index));
}
-static void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
+static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
{
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
}
-static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -73,7 +73,7 @@ static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -85,7 +85,7 @@ static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
-static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -98,8 +98,8 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
/* family 10 only, for reg > 0xFF */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
-static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
- u32 val)
+static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos,
+ u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = Get_NB32(fam10_dev, reg_pos);
@@ -114,7 +114,7 @@ static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 m
#endif
-static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
+static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
u8 val)
{
u8 reg_old, reg;
@@ -126,7 +126,7 @@ static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask,
}
}
-static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
+static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
u32 val)
{
u32 reg_old, reg;
@@ -155,7 +155,7 @@ static u8 cpu_core_number(void)
}
#endif
-static u8 get_nb_rev(device_t nb_dev)
+static u8 get_nb_rev(pci_devfn_t nb_dev)
{
u8 reg;
reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */
@@ -203,7 +203,7 @@ static void rs780_htinit(void)
/*
* About HT, it has been done in enumerate_ht_chain().
*/
- device_t cpu_f0, rs780_f0, clk_f1;
+ pci_devfn_t cpu_f0, rs780_f0, clk_f1;
u32 reg;
u8 cpu_ht_freq, ibias;
@@ -299,7 +299,7 @@ static void rs780_htinit(void)
*******************************************************/
static void k8_optimization(void)
{
- device_t k8_f0, k8_f2, k8_f3;
+ pci_devfn_t k8_f0, k8_f2, k8_f3;
msr_t msr;
printk(BIOS_INFO, "k8_optimization()\n");
@@ -341,7 +341,7 @@ static void k8_optimization(void)
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
static void fam10_optimization(void)
{
- device_t cpu_f0, cpu_f2, cpu_f3;
+ pci_devfn_t cpu_f0, cpu_f2, cpu_f3;
u32 val;
printk(BIOS_INFO, "fam10_optimization()\n");
@@ -406,7 +406,7 @@ static void fam10_optimization(void)
/*****************************************
* rs780_por_pcicfg_init()
*****************************************/
-static void rs780_por_pcicfg_init(device_t nb_dev)
+static void rs780_por_pcicfg_init(pci_devfn_t nb_dev)
{
/* enable PCI Memory Access */
set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
@@ -456,7 +456,7 @@ static void rs780_por_pcicfg_init(device_t nb_dev)
set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x02);
}
-static void rs780_por_mc_index_init(device_t nb_dev)
+static void rs780_por_mc_index_init(pci_devfn_t nb_dev)
{
set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F);
set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060);
@@ -467,7 +467,7 @@ static void rs780_por_mc_index_init(device_t nb_dev)
set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E);
}
-static void rs780_por_misc_index_init(device_t nb_dev)
+static void rs780_por_misc_index_init(pci_devfn_t nb_dev)
{
/* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
* Block non-snoop DMA request if PMArbDis is set.
@@ -524,7 +524,7 @@ static void rs780_por_misc_index_init(device_t nb_dev)
/*****************************************
* Some setting is from rpr. Some is from CIMx.
*****************************************/
-static void rs780_por_htiu_index_init(device_t nb_dev)
+static void rs780_por_htiu_index_init(pci_devfn_t nb_dev)
{
#if 0 /* get from rpr. */
set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17);
@@ -583,7 +583,7 @@ static void rs780_por_htiu_index_init(device_t nb_dev)
* POR: Power On Reset
* RPR: Register Programming Requirements
*****************************************/
-static void rs780_por_init(device_t nb_dev)
+static void rs780_por_init(pci_devfn_t nb_dev)
{
printk(BIOS_INFO, "rs780_por_init\n");
/* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */
@@ -621,7 +621,7 @@ static void rs780_before_pci_init(void)
static void rs780_early_setup(void)
{
- device_t nb_dev = PCI_DEV(0, 0, 0);
+ pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);
printk(BIOS_INFO, "rs780_early_setup()\n");
/* The printk(BIOS_INFO, s) below cause the system unstable. */
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