[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Add PM methods to power gate PCIe

[Vaibhav Shankar (vaibhav.shankar@intel.com)]

Vaibhav Shankar (vaibhav.shankar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16351

-gerrit

commit c7df77f7e276a3524d15af03775da842283c6c12
Author: Vaibhav Shankar <vaibhav.shankar at intel.com>
Date:   Tue Aug 23 17:56:17 2016 -0700

    soc/intel/apollolake: Add PM methods to power gate PCIe
    
    Implement _ON/_OFF methods to power gate PCIe during S0ix
    entry. Added PERST_0 assertion/de-assertion methods.
    
    BUG=chrome-os-partner:55877
    TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
    System should resume with PCIE and wifi functional.
    
    Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19
    Signed-off-by: Vaibhav Shankar <vaibhav.shankar at intel.com>
---
 src/soc/intel/apollolake/acpi/gpio.asl        |  27 ++++++
 src/soc/intel/apollolake/acpi/pcie.asl        | 123 ++++++++++++++++++++++++++
 src/soc/intel/apollolake/acpi/southbridge.asl |   3 +
 3 files changed, 153 insertions(+)

diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index 03b8edd..21a0b2f 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 #include <soc/gpio_defs.h>
+#include "gpiolib.asl"
 
 scope (\_SB) {
 
@@ -141,6 +142,32 @@ scope (\_SB) {
 			Return(0xf)
 		}
 	}
+
+	/* PERST Assertion
+	 * Note: PERST is Active High
+	 */
+	Method (PRAS, 0x0, Serialized)
+	{
+		/*
+		 * Assert PERST
+		 * local1 - to toggle Tx pin of Dw0
+		 */
+		Store (\_SB.GPC0(\PRAD), Local1)
+		Or (Local1, PAD_CFG0_TX_STATE, Local1)
+		\_SB.SPC0 (\PRAD, Local1)
+	}
+
+	/* PERST DE-Assertion */
+	Method (PRDA, 0x0, Serialized)
+	{
+		/*
+		 * De-assert PERST
+		 * local1 - to toggle Tx pin of Dw0
+		 */
+		Store (\_SB.GPC0 (\PRAD), Local1)
+		And (Local1, ~PAD_CFG0_TX_STATE, Local1)
+		\_SB.SPC0 (\PRAD, Local1)
+	}
 }
 
 Scope(\_GPE)
diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl
new file mode 100644
index 0000000..0bdec4e
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pcie.asl
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (RP01)
+{
+	Name (_ADR, 0x00140000)
+	Name (_DDN, "PCIe-B 0")
+	Name (PDST, 0) /* present Detect status */
+
+	/* lowest D-state supported by
+	 * PCIe root port during S0 state
+	 */
+	Name (_S0W, 4)
+
+	/* Dynamic Opregion needed to access registers
+	 * when the controller is in D3 cold
+	 */
+	OperationRegion(PX02, PCI_Config, 0x0, 0x380)
+	Field(PX02, AnyAcc, NoLock, Preserve)
+	{
+		Offset(0x5A),	/* SLSTS- SLot status Register */
+		, 6,
+		PDS, 1,		/* 6, Presence detect Change */
+		Offset(0xE2),	/* RPPGEN - Root Port Power Gating Enable */
+		, 2,
+		L23E, 1,	/* 2, L23_Rdy Entry Request (L23ER) */
+		L23R, 1,	/* 3, L23_Rdy to Detect Transition (L23R2DT) */
+		Offset(0xF4),	/* BLKPLLEN */
+		, 10,
+		BPLL, 1,
+		Offset(0x338),
+		, 26,
+		BDQA, 1		/* BLKDQDA */
+	}
+
+
+	PowerResource (PXP, 0, 0)
+	{
+		/* Define the PowerResource for PCIe slot */
+		Method (_STA, 0, Serialized)
+		{
+			Store (PDS, PDST)
+			If (LEqual (PDS, 1)) {
+					Return (0xf)
+			} Else {
+					Return (0)
+				}
+		}
+
+		Method (_ON, 0, Serialized)
+		{
+			If (LEqual (PDST, 1)) {
+				/* Enter this condition if device
+				 * is connected
+				 */
+
+				/* De-assert PERST */
+				\_SB.PRDA()
+
+				Store (0, BDQA) /* Set BLKDQDA to 0 */
+				Store (0, BPLL) /* Set BLKPLLEN to 0 */
+
+				/* Set L23_Rdy to Detect Transition
+				 * (L23R2DT)
+				 */
+				Store (1, L23R)
+				Sleep (16)
+				Store (0, Local0)
+
+				/* Delay for transition Detect
+				 * and link to train
+				 */
+				While (L23R) {
+					If (Lgreater (Local0, 4)) {
+						Break
+					}
+					Sleep (16)
+					Increment (Local0)
+				}
+			} /* End PDS condition check */
+		}
+
+		Method (_OFF, 0, Serialized)
+		{
+			/* Set L23_Rdy Entry Request (L23ER) */
+			If (LEqual (PDST, 1)) {
+				/* enter this condition if device
+				 * is connected
+				 */
+				Store (1, L23E)
+				Sleep (16)
+				Store (0, Local0)
+				While (L23E) {
+					If (Lgreater (Local0, 4)) {
+						Break
+					}
+					Sleep (16)
+					Increment (Local0)
+				}
+				Store (1, BDQA) /* Set BLKDQDA to 1 */
+				Store (1, BPLL) /* Set BLKPLLEN to 1 */
+
+				/* Assert PERST */
+				\_SB.PRAS()
+			} /* End PDS condition check */
+		} /* End of Method_OFF */
+	} /* End PXP */
+
+	Name(_PR0, Package() { PXP })
+	Name(_PR3, Package() { PXP })
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 391a531..d7ced0f 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -17,6 +17,9 @@
 
 #include <soc/gpe.h>
 
+/* PCIE device */
+#include "pcie.asl"
+
 /* LPSS device */
 #include "lpss.asl"