[coreboot-gerrit] New patch to review for coreboot: nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC

HAOUAS Elyes (ehaouas@noos.fr) gerrit at coreboot.org
Sun Oct 30 18:36:49 CET 2016


HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17191

-gerrit

commit 5ec99d0e9b37b23c7641cf8fa005d05c8dca2b54
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sun Oct 30 18:30:21 2016 +0100

    nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC
    
    Change-Id: I3d54c88af897a71db757d00288f3968ed2c19151
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 3rdparty/blobs                          | 2 +-
 3rdparty/chromeec                       | 2 +-
 3rdparty/vboot                          | 2 +-
 src/northbridge/intel/i945/early_init.c | 3 +++
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/3rdparty/blobs b/3rdparty/blobs
index 8ad2d63..b0eeddd 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 8ad2d6385652e14b6f0d35ab9b474c31ddeb1773
+Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2
diff --git a/3rdparty/chromeec b/3rdparty/chromeec
index ea1a869..83b6d69 160000
--- a/3rdparty/chromeec
+++ b/3rdparty/chromeec
@@ -1 +1 @@
-Subproject commit ea1a8699e96425806abdd532d04da254ae093f6e
+Subproject commit 83b6d69732f782e2b295153f959ec36d4a56c024
diff --git a/3rdparty/vboot b/3rdparty/vboot
index ea72ee4..46b77fb 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit ea72ee454aea5e0f378275fe7114cf683b7db938
+Subproject commit 46b77fb2f04941c869c3a98cd17e9209c36b2917
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 4373167..17fd5a4 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -132,6 +132,9 @@ static void i945_detect_chipset(void)
 	case 0:
 		printk(BIOS_DEBUG, "up to DDR2-667");
 		break;
+	case 2:
+		printk(BIOS_DEBUG, "up to DDR2-667");
+		break;
 	case 3:
 		printk(BIOS_DEBUG, "up to DDR2-533");
 		break;



More information about the coreboot-gerrit mailing list