[coreboot-gerrit] Patch merged into coreboot/master: nb/intel/sandybridge/gma: Always initialize DP buffer translation

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 07e206a6466197487f9f877ee6f5e7a7bec751a2
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed Oct 19 15:20:17 2016 +0200

    nb/intel/sandybridge/gma: Always initialize DP buffer translation
    
    These settings should be always made by the firmware, no matter if we
    set up graphics or not. It looks like Linux doesn't even know these
    registers.
    
    The values are taken from the PRMs for Sandy Bridge and Ivy Bridge [1,
    2]. They match the settings that were done in the native graphics path
    for Ivy Bridge. I expect the differences to be an update (i.e. the set-
    tings we did on the Sandy Bridge path were just outdated). Also, these
    settings affect the PCH and not the CPU which are independent from each
    other.
    
    [1] Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM)
        Volume 3 Part 3: PCH Display Registers (SandyBridge)
        Doc Ref #: IHD-OS-V3 Pt3 – 05 11
        https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part3.pdf
    
    [2] Intel ® OpenSource HD Graphics Programmer’s Reference Manual (PRM)
        Volume 3 Part 4: South Display Engine Registers (Ivy Bridge)
        Doc Ref #: IHD-OS-V3 Pt 4 – 05 12
        https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part4.pdf
    
    Change-Id: I83cc90c7558b93273a727f332fb0d8ced47ed70e
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
    Reviewed-on: https://review.coreboot.org/17073
    Tested-by: build bot (Jenkins)
    Reviewed-by: Arthur Heymans <arthur at aheymans.xyz>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/17073 for details.

-gerrit