[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/common: Add reset.c to postcar
gerrit at coreboot.org
gerrit at coreboot.org
Sat Oct 29 00:23:14 CEST 2016
the following patch was just integrated into master:
commit 566feddeceb421ba6480bcee94f87bc4c95c6196
Author: Furquan Shaikh <furquan at chromium.org>
Date: Fri Oct 28 14:55:46 2016 -0700
soc/intel/common: Add reset.c to postcar
ramstage_cache_invalid which was added in
I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112)
requires hard_reset to be defined in postcar stage.
BUG=None
BRANCH=None
TEST=Compiles successfully for reef.
Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
Reviewed-on: https://review.coreboot.org/17182
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/17182 for details.
-gerrit
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