[coreboot-gerrit] New patch to review for coreboot: sb/nvidia/mcp55: Remove whitespace

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17173

-gerrit

commit 25d7a30dd45ce80c5f9a000f995e709be0e2afa6
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Fri Oct 28 10:18:04 2016 +0200

    sb/nvidia/mcp55: Remove whitespace
    
    Change-Id: Id35803b9fe22375ac0e0d11ae0f1e9b2f3795b0d
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/southbridge/nvidia/mcp55/early_setup_car.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 7f1d03b..c98c28a 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -150,7 +150,8 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
 			      unsigned *devn, unsigned *io_base,
 			      unsigned *pci_e_x)
 {
-    static const unsigned int ctrl_conf_1[] = {
+
+static const unsigned int ctrl_conf_1[] = {
 	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
 	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
 	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
@@ -197,9 +198,9 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
 	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
 	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
 	RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040, /* Enable bridge mode. */
-    };
+};
 
-    static const unsigned int ctrl_conf_1_1[] = {
+static const unsigned int ctrl_conf_1_1[] = {
 	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
 	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
 	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
@@ -209,9 +210,9 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
 	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
 	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
 	RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
-    };
+};
 
-    static const unsigned int ctrl_conf_mcp55_only[] = {
+static const unsigned int ctrl_conf_mcp55_only[] = {
 	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
 	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
 	RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
@@ -265,16 +266,16 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2),
 #endif
-    };
+};
 
-    static const unsigned int ctrl_conf_master_only[] = {
+static const unsigned int ctrl_conf_master_only[] = {
 	RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
 
 	/* Master MCP55???? YHLU */
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3 << 2), (0 << 2),
-    };
+};
 
-    static const unsigned int ctrl_conf_2[] = {
+static const unsigned int ctrl_conf_2[] = {
 	/* I didn't put PCI-E related stuff here. */
 
 	RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
@@ -290,7 +291,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)),
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
 #endif
-    };
+};
 
 	int j, i;