[coreboot-gerrit] New patch to review for coreboot: northbridge/amd: Update all names and IDs for 00670F00
Marc Jones (marc@marcjonesconsulting.com)
gerrit at coreboot.org
Wed Oct 26 05:14:32 CEST 2016
Marc Jones (marc at marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17143
-gerrit
commit 20f25d0dad1d858fa5e8f0283125ecafb3ea4d5e
Author: Marc Jones <marcj303 at gmail.com>
Date: Tue Sep 20 20:30:17 2016 -0600
northbridge/amd: Update all names and IDs for 00670F00
Modify the new Stoney support files to match the APU's IDs and codename.
Original-Signed-off-by: Marc Jones <marcj303 at gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
(cherry picked from commit de626730758def76e558294762a06d8ec9950cb9)
Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
src/northbridge/amd/pi/00670F00/Kconfig | 8 ++++----
src/northbridge/amd/pi/00670F00/chip.h | 6 +++---
src/northbridge/amd/pi/00670F00/dimmSpd.c | 2 +-
src/northbridge/amd/pi/00670F00/northbridge.c | 10 +++++-----
src/northbridge/amd/pi/Kconfig | 1 +
src/northbridge/amd/pi/Makefile.inc | 1 +
6 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig
index f5d234d..4204241 100644
--- a/src/northbridge/amd/pi/00670F00/Kconfig
+++ b/src/northbridge/amd/pi/00670F00/Kconfig
@@ -12,11 +12,11 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
-config NORTHBRIDGE_AMD_PI_00660F01
+config NORTHBRIDGE_AMD_PI_00670F00
bool
select MMCONF_SUPPORT
-if NORTHBRIDGE_AMD_PI_00660F01
+if NORTHBRIDGE_AMD_PI_00670F00
config HW_MEM_HOLE_SIZEK
hex
@@ -36,13 +36,13 @@ config MMCONF_BUS_NUMBER
config VGA_BIOS_ID
string
- default "1002,9870"
+ default "1002,98e4"
help
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
config VGA_BIOS_FILE
string
- default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin"
+ default "3rdparty/blobs/northbridge/amd/00670F00/VBIOS.bin"
endif
diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h
index ab0e3d2..917bc65 100644
--- a/src/northbridge/amd/pi/00670F00/chip.h
+++ b/src/northbridge/amd/pi/00670F00/chip.h
@@ -13,10 +13,10 @@
* GNU General Public License for more details.
*/
-#ifndef _PI_FAM15CZ_CHIP_H_
-#define _PI_FAM15CZ_CHIP_H_
+#ifndef _PI_FAM15ST_CHIP_H_
+#define _PI_FAM15ST_CHIP_H_
-struct northbridge_amd_pi_00660F01_config
+struct northbridge_amd_pi_00670F00_config
{
u8 spdAddrLookup[2][2][4];
};
diff --git a/src/northbridge/amd/pi/00670F00/dimmSpd.c b/src/northbridge/amd/pi/00670F00/dimmSpd.c
index 5c81f36..2880d4e 100644
--- a/src/northbridge/amd/pi/00670F00/dimmSpd.c
+++ b/src/northbridge/amd/pi/00670F00/dimmSpd.c
@@ -28,7 +28,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
{
int spdAddress;
ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
- ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
+ ROMSTAGE_CONST struct northbridge_amd_pi_00670F00_config *config = dev->chip_info;
if ((dev == 0) || (config == 0))
return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c
index 1caecf9..51d6960 100644
--- a/src/northbridge/amd/pi/00670F00/northbridge.c
+++ b/src/northbridge/amd/pi/00670F00/northbridge.c
@@ -582,7 +582,7 @@ static struct device_operations northbridge_operations = {
static const struct pci_driver family15_northbridge __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT,
+ .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,
};
static void fam15_finalize(void *chip_info)
@@ -600,7 +600,7 @@ static void fam15_finalize(void *chip_info)
pci_write_config32(dev, 0x60, value);
}
-struct chip_operations northbridge_amd_pi_00660F01_ops = {
+struct chip_operations northbridge_amd_pi_00670F00_ops = {
CHIP_NAME("AMD FAM15 Northbridge")
.enable_dev = 0,
.final = fam15_finalize,
@@ -1140,8 +1140,8 @@ static void root_complex_enable_dev(struct device *dev)
}
}
-struct chip_operations northbridge_amd_pi_00660F01_root_complex_ops = {
- CHIP_NAME("AMD FAM16 Root Complex")
+struct chip_operations northbridge_amd_pi_00670F00_root_complex_ops = {
+ CHIP_NAME("AMD FAM15 Root Complex")
.enable_dev = root_complex_enable_dev,
};
@@ -1152,7 +1152,7 @@ u32 map_oprom_vendev(u32 vendev)
{
u32 new_vendev;
new_vendev =
- ((0x10029870 <= vendev) && (vendev <= 0x1002987F)) ? 0x10029870 : vendev;
+ ((0x100298E0 <= vendev) && (vendev <= 0x100298EF)) ? 0x100298E0 : vendev;
if (vendev != new_vendev)
printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev);
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
index cb72416..04dd73c 100644
--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
@@ -30,6 +30,7 @@ config S3_VGA_ROM_RUN
source src/northbridge/amd/pi/00630F01/Kconfig
source src/northbridge/amd/pi/00730F01/Kconfig
+source src/northbridge/amd/pi/00670F00/Kconfig
source src/northbridge/amd/pi/00660F01/Kconfig
config HW_MEM_HOLE_SIZEK
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc
index 5c2d8e0..a16c43e 100644
--- a/src/northbridge/amd/pi/Makefile.inc
+++ b/src/northbridge/amd/pi/Makefile.inc
@@ -17,6 +17,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y)
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00670F00) += 00670F00
subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
romstage-y += agesawrapper.c
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