[coreboot-gerrit] Patch set updated for coreboot: util/inteltool: Use tabs for indents
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Fri Oct 14 08:48:20 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17025
-gerrit
commit 62bcfec90871ae7154716d62264327dc503f0493
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Thu Oct 13 21:55:08 2016 +0200
util/inteltool: Use tabs for indents
Change-Id: I9d27c276053c51021166f4b22d150060e415d08f
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
util/inteltool/cpu.c | 705 ++++++++++++++++++++++-----------------------
util/inteltool/inteltool.h | 6 +-
util/inteltool/pcie.c | 90 +++---
3 files changed, 399 insertions(+), 402 deletions(-)
diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index 9bdc1eb..bdec9ea 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -815,191 +815,191 @@ int print_intel_core_msrs(void)
*/
};
- static const msr_entry_t model6_atom_per_core_msrs[] = {
- { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
- { 0x0010, "IA32_TIME_STAMP_COUNTER" },
- { 0x001b, "IA32_APIC_BASE" },
- { 0x003a, "IA32_FEATURE_CONTROL" },
- { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
- { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
- { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
- { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
- { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
- { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
- { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
- { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
- { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
- { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
- { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
- { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
- { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
- { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
- { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
- { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
- /* Write register */
- /*
- { 0x0079, "IA32_BIOS_UPDT_TRIG" },
- */
- { 0x008b, "IA32_BIOS_SIGN_ID" },
- { 0x00c1, "IA32_PMC0" },
- { 0x00c2, "IA32_PMC1" },
- { 0x00e7, "IA32_MPERF" },
- { 0x00e8, "IA32_APERF" },
- { 0x0174, "IA32_SYSENTER_CS" },
- { 0x0175, "IA32_SYSENTER_ESP" },
- { 0x0176, "IA32_SYSENTER_EIP" },
- { 0x017a, "IA32_MCG_STATUS" },
- { 0x0186, "IA32_PERF_EVNTSEL0" },
- { 0x0187, "IA32_PERF_EVNTSEL1" },
- { 0x0199, "IA32_PERF_CONTROL" },
- { 0x019a, "IA32_CLOCK_MODULATION" },
- { 0x019b, "IA32_THERM_INTERRUPT" },
- { 0x019c, "IA32_THERM_STATUS" },
- { 0x01a0, "IA32_MISC_ENABLES" },
- { 0x01c9, "MSR_LASTBRANCH_TOS" },
- { 0x01d9, "IA32_DEBUGCTL" },
- { 0x01dd, "MSR_LER_FROM_LIP" },
- { 0x01de, "MSR_LER_TO_LIP" },
- { 0x0277, "IA32_PAT" },
- { 0x0309, "IA32_FIXED_CTR0" },
- { 0x030a, "IA32_FIXED_CTR1" },
- { 0x030b, "IA32_FIXED_CTR2" },
- { 0x038d, "IA32_FIXED_CTR_CTRL" },
- { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
- { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
- { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
- { 0x03f1, "MSR_PEBS_ENABLE" },
- { 0x0480, "IA32_VMX_BASIC" },
- { 0x0481, "IA32_VMX_PINBASED_CTLS" },
- { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
- { 0x0483, "IA32_VMX_EXIT_CTLS" },
- { 0x0484, "IA32_VMX_ENTRY_CTLS" },
- { 0x0485, "IA32_VMX_MISC" },
- { 0x0486, "IA32_VMX_CR0_FIXED0" },
- { 0x0487, "IA32_VMX_CR0_FIXED1" },
- { 0x0488, "IA32_VMX_CR4_FIXED0" },
- { 0x0489, "IA32_VMX_CR4_FIXED1" },
- { 0x048a, "IA32_VMX_VMCS_ENUM" },
- { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
- { 0x0600, "IA32_DS_AREA" },
- };
+static const msr_entry_t model6_atom_per_core_msrs[] = {
+ { 0x0006, "IA32_MONITOR_FILTER_SIZE" },
+ { 0x0010, "IA32_TIME_STAMP_COUNTER" },
+ { 0x001b, "IA32_APIC_BASE" },
+ { 0x003a, "IA32_FEATURE_CONTROL" },
+ { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
+ { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
+ { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
+ { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
+ { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
+ { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
+ { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
+ { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
+ { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
+ { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
+ { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
+ { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
+ { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
+ { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
+ { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
+ { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
+ /* Write register */
+ /*
+ { 0x0079, "IA32_BIOS_UPDT_TRIG" },
+ */
+ { 0x008b, "IA32_BIOS_SIGN_ID" },
+ { 0x00c1, "IA32_PMC0" },
+ { 0x00c2, "IA32_PMC1" },
+ { 0x00e7, "IA32_MPERF" },
+ { 0x00e8, "IA32_APERF" },
+ { 0x0174, "IA32_SYSENTER_CS" },
+ { 0x0175, "IA32_SYSENTER_ESP" },
+ { 0x0176, "IA32_SYSENTER_EIP" },
+ { 0x017a, "IA32_MCG_STATUS" },
+ { 0x0186, "IA32_PERF_EVNTSEL0" },
+ { 0x0187, "IA32_PERF_EVNTSEL1" },
+ { 0x0199, "IA32_PERF_CONTROL" },
+ { 0x019a, "IA32_CLOCK_MODULATION" },
+ { 0x019b, "IA32_THERM_INTERRUPT" },
+ { 0x019c, "IA32_THERM_STATUS" },
+ { 0x01a0, "IA32_MISC_ENABLES" },
+ { 0x01c9, "MSR_LASTBRANCH_TOS" },
+ { 0x01d9, "IA32_DEBUGCTL" },
+ { 0x01dd, "MSR_LER_FROM_LIP" },
+ { 0x01de, "MSR_LER_TO_LIP" },
+ { 0x0277, "IA32_PAT" },
+ { 0x0309, "IA32_FIXED_CTR0" },
+ { 0x030a, "IA32_FIXED_CTR1" },
+ { 0x030b, "IA32_FIXED_CTR2" },
+ { 0x038d, "IA32_FIXED_CTR_CTRL" },
+ { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
+ { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
+ { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
+ { 0x03f1, "MSR_PEBS_ENABLE" },
+ { 0x0480, "IA32_VMX_BASIC" },
+ { 0x0481, "IA32_VMX_PINBASED_CTLS" },
+ { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
+ { 0x0483, "IA32_VMX_EXIT_CTLS" },
+ { 0x0484, "IA32_VMX_ENTRY_CTLS" },
+ { 0x0485, "IA32_VMX_MISC" },
+ { 0x0486, "IA32_VMX_CR0_FIXED0" },
+ { 0x0487, "IA32_VMX_CR0_FIXED1" },
+ { 0x0488, "IA32_VMX_CR4_FIXED0" },
+ { 0x0489, "IA32_VMX_CR4_FIXED1" },
+ { 0x048a, "IA32_VMX_VMCS_ENUM" },
+ { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
+ { 0x0600, "IA32_DS_AREA" },
+};
- static const msr_entry_t model20650_global_msrs[] = {
- { 0x0000, "IA32_P5_MC_ADDR" },
- { 0x0001, "IA32_P5_MC_TYPE" },
- { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
- { 0x0017, "IA32_PLATFORM_ID" },
- { 0x002a, "MSR_EBC_HARD_POWERON" },
+static const msr_entry_t model20650_global_msrs[] = {
+ { 0x0000, "IA32_P5_MC_ADDR" },
+ { 0x0001, "IA32_P5_MC_TYPE" },
+ { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
+ { 0x0017, "IA32_PLATFORM_ID" },
+ { 0x002a, "MSR_EBC_HARD_POWERON" },
// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" },
- { 0x00ce, "IA32_MSR_PLATFORM_INFO" },
- { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" },
- { 0x019c, "IA32_THERM_STATUS" },
- { 0x019d, "MSR_THERM2_CTL" },
- { 0x01a0, "IA32_MISC_ENABLE" },
- { 0x0200, "IA32_MTRR_PHYSBASE0" },
- { 0x0201, "IA32_MTRR_PHYSMASK0" },
- { 0x0202, "IA32_MTRR_PHYSBASE1" },
- { 0x0203, "IA32_MTRR_PHYSMASK1" },
- { 0x0204, "IA32_MTRR_PHYSBASE2" },
- { 0x0205, "IA32_MTRR_PHYSMASK2" },
- { 0x0206, "IA32_MTRR_PHYSBASE3" },
- { 0x0207, "IA32_MTRR_PHYSMASK3" },
- { 0x0208, "IA32_MTRR_PHYSBASE4" },
- { 0x0209, "IA32_MTRR_PHYSMASK4" },
- { 0x020a, "IA32_MTRR_PHYSBASE5" },
- { 0x020b, "IA32_MTRR_PHYSMASK5" },
- { 0x020c, "IA32_MTRR_PHYSBASE6" },
- { 0x020d, "IA32_MTRR_PHYSMASK6" },
- { 0x020e, "IA32_MTRR_PHYSBASE7" },
- { 0x020f, "IA32_MTRR_PHYSMASK7" },
- { 0x0250, "IA32_MTRR_FIX64K_00000" },
- { 0x0258, "IA32_MTRR_FIX16K_80000" },
- { 0x0259, "IA32_MTRR_FIX16K_A0000" },
- { 0x0268, "IA32_MTRR_FIX4K_C0000" },
- { 0x0269, "IA32_MTRR_FIX4K_C8000" },
- { 0x026a, "IA32_MTRR_FIX4K_D0000" },
- { 0x026b, "IA32_MTRR_FIX4K_D8000" },
- { 0x026c, "IA32_MTRR_FIX4K_E0000" },
- { 0x026d, "IA32_MTRR_FIX4K_E8000" },
- { 0x026e, "IA32_MTRR_FIX4K_F0000" },
- { 0x026f, "IA32_MTRR_FIX4K_F8000" },
- { 0x02ff, "IA32_MTRR_DEF_TYPE" },
- { 0x0300, "MSR_BPU_COUNTER0" },
- { 0x0301, "MSR_BPU_COUNTER1" },
- /* Skipped through 0x3ff for now*/
+ { 0x00ce, "IA32_MSR_PLATFORM_INFO" },
+ { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" },
+ { 0x019c, "IA32_THERM_STATUS" },
+ { 0x019d, "MSR_THERM2_CTL" },
+ { 0x01a0, "IA32_MISC_ENABLE" },
+ { 0x0200, "IA32_MTRR_PHYSBASE0" },
+ { 0x0201, "IA32_MTRR_PHYSMASK0" },
+ { 0x0202, "IA32_MTRR_PHYSBASE1" },
+ { 0x0203, "IA32_MTRR_PHYSMASK1" },
+ { 0x0204, "IA32_MTRR_PHYSBASE2" },
+ { 0x0205, "IA32_MTRR_PHYSMASK2" },
+ { 0x0206, "IA32_MTRR_PHYSBASE3" },
+ { 0x0207, "IA32_MTRR_PHYSMASK3" },
+ { 0x0208, "IA32_MTRR_PHYSBASE4" },
+ { 0x0209, "IA32_MTRR_PHYSMASK4" },
+ { 0x020a, "IA32_MTRR_PHYSBASE5" },
+ { 0x020b, "IA32_MTRR_PHYSMASK5" },
+ { 0x020c, "IA32_MTRR_PHYSBASE6" },
+ { 0x020d, "IA32_MTRR_PHYSMASK6" },
+ { 0x020e, "IA32_MTRR_PHYSBASE7" },
+ { 0x020f, "IA32_MTRR_PHYSMASK7" },
+ { 0x0250, "IA32_MTRR_FIX64K_00000" },
+ { 0x0258, "IA32_MTRR_FIX16K_80000" },
+ { 0x0259, "IA32_MTRR_FIX16K_A0000" },
+ { 0x0268, "IA32_MTRR_FIX4K_C0000" },
+ { 0x0269, "IA32_MTRR_FIX4K_C8000" },
+ { 0x026a, "IA32_MTRR_FIX4K_D0000" },
+ { 0x026b, "IA32_MTRR_FIX4K_D8000" },
+ { 0x026c, "IA32_MTRR_FIX4K_E0000" },
+ { 0x026d, "IA32_MTRR_FIX4K_E8000" },
+ { 0x026e, "IA32_MTRR_FIX4K_F0000" },
+ { 0x026f, "IA32_MTRR_FIX4K_F8000" },
+ { 0x02ff, "IA32_MTRR_DEF_TYPE" },
+ { 0x0300, "MSR_BPU_COUNTER0" },
+ { 0x0301, "MSR_BPU_COUNTER1" },
+ /* Skipped through 0x3ff for now*/
- /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
- * set in MCX_STATUS */
- { 0x400, "IA32_MC0_CTL" },
- { 0x401, "IA32_MC0_STATUS" },
- { 0x402, "IA32_MC0_ADDR" },
- { 0x403, "IA32_MC0_MISC" },
- { 0x404, "IA32_MC1_CTL" },
- { 0x405, "IA32_MC1_STATUS" },
- { 0x406, "IA32_MC1_ADDR" },
- { 0x407, "IA32_MC1_MISC" },
- { 0x408, "IA32_MC2_CTL" },
- { 0x409, "IA32_MC2_STATUS" },
- { 0x40a, "IA32_MC2_ADDR" },
- { 0x40c, "IA32_MC3_CTL" },
- { 0x40d, "IA32_MC3_STATUS" },
- { 0x40e, "IA32_MC3_ADDR" },
- { 0x410, "IA32_MC4_CTL" },
- { 0x411, "IA32_MC4_STATUS" },
- };
+ /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being
+ * set in MCX_STATUS */
+ { 0x400, "IA32_MC0_CTL" },
+ { 0x401, "IA32_MC0_STATUS" },
+ { 0x402, "IA32_MC0_ADDR" },
+ { 0x403, "IA32_MC0_MISC" },
+ { 0x404, "IA32_MC1_CTL" },
+ { 0x405, "IA32_MC1_STATUS" },
+ { 0x406, "IA32_MC1_ADDR" },
+ { 0x407, "IA32_MC1_MISC" },
+ { 0x408, "IA32_MC2_CTL" },
+ { 0x409, "IA32_MC2_STATUS" },
+ { 0x40a, "IA32_MC2_ADDR" },
+ { 0x40c, "IA32_MC3_CTL" },
+ { 0x40d, "IA32_MC3_STATUS" },
+ { 0x40e, "IA32_MC3_ADDR" },
+ { 0x410, "IA32_MC4_CTL" },
+ { 0x411, "IA32_MC4_STATUS" },
+};
- static const msr_entry_t model20650_per_core_msrs[] = {
- { 0x0010, "IA32_TIME_STAMP_COUNTER" },
- { 0x001b, "IA32_APIC_BASE" },
- { 0x003a, "IA32_FEATURE_CONTROL" },
- { 0x008b, "IA32_BIOS_SIGN_ID" },
- { 0x009b, "IA32_SMM_MONITOR_CTL" },
- { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" },
- { 0x00fe, "IA32_MTRRCAP" },
- { 0x0174, "IA32_SYSENTER_CS" },
- { 0x0175, "IA32_SYSENTER_ESP" },
- { 0x0176, "IA32_SYSENTER_EIP" },
- { 0x0179, "IA32_MCG_CAP" },
- { 0x017a, "IA32_MCG_STATUS" },
- { 0x0186, "MSR_MCG_RBP" },
- { 0x0187, "MSR_MCG_RSP" },
- { 0x0188, "MSR_MCG_RFLAGS" },
- { 0x0189, "MSR_MCG_RIP" },
- { 0x0194, "MSR_MCG_R12" },
- { 0x0198, "IA32_PERF_STATUS" },
- { 0x0199, "IA32_PERF_CTL" },
- { 0x019a, "IA32_CLOCK_MODULATION" },
- { 0x019b, "IA32_THERM_INTERRUPT" },
- { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
- { 0x01aa, "IA32_MISC_PWR_MGMT" },
- { 0x01d9, "MSR_DEBUGCTLA" },
- { 0x01fc, "MSR_POWER_CTL" },
- { 0x0277, "IA32_PAT" },
- /** Virtualization
- { 0x480, "IA32_VMX_BASIC" },
- through
- { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
- Not implemented in my CPU
- */
- { 0x0600, "IA32_DS_AREA" },
- /* 0x0680 - 0x06cf Branch Records Skipped */
+static const msr_entry_t model20650_per_core_msrs[] = {
+ { 0x0010, "IA32_TIME_STAMP_COUNTER" },
+ { 0x001b, "IA32_APIC_BASE" },
+ { 0x003a, "IA32_FEATURE_CONTROL" },
+ { 0x008b, "IA32_BIOS_SIGN_ID" },
+ { 0x009b, "IA32_SMM_MONITOR_CTL" },
+ { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" },
+ { 0x00fe, "IA32_MTRRCAP" },
+ { 0x0174, "IA32_SYSENTER_CS" },
+ { 0x0175, "IA32_SYSENTER_ESP" },
+ { 0x0176, "IA32_SYSENTER_EIP" },
+ { 0x0179, "IA32_MCG_CAP" },
+ { 0x017a, "IA32_MCG_STATUS" },
+ { 0x0186, "MSR_MCG_RBP" },
+ { 0x0187, "MSR_MCG_RSP" },
+ { 0x0188, "MSR_MCG_RFLAGS" },
+ { 0x0189, "MSR_MCG_RIP" },
+ { 0x0194, "MSR_MCG_R12" },
+ { 0x0198, "IA32_PERF_STATUS" },
+ { 0x0199, "IA32_PERF_CTL" },
+ { 0x019a, "IA32_CLOCK_MODULATION" },
+ { 0x019b, "IA32_THERM_INTERRUPT" },
+ { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific
+ { 0x01aa, "IA32_MISC_PWR_MGMT" },
+ { 0x01d9, "MSR_DEBUGCTLA" },
+ { 0x01fc, "MSR_POWER_CTL" },
+ { 0x0277, "IA32_PAT" },
+ /** Virtualization
+ { 0x480, "IA32_VMX_BASIC" },
+ through
+ { 0x48b, "IA32_VMX_PROCBASED_CTLS2" },
+ Not implemented in my CPU
+ */
+ { 0x0600, "IA32_DS_AREA" },
+ /* 0x0680 - 0x06cf Branch Records Skipped */
- { 0x3a, "IA32_FEATURE_CONTROL" },
- { 0x13c, "MSR_FEATURE_CONFIG" },
- { 0x194, "MSR_FLEX_RATIO" },
- { 0x1a0, "IA32_MISC_ENABLE" },
- { 0x1a2, "MSR_TEMPERATURE_TARGET" },
- { 0x199, "IA32_PERF_CTL" },
- { 0x19b, "IA32_THERM_INTERRUPT" },
- { 0x401, "IA32_MC0_STATUS" },
- { 0x2e, "MSR_PIC_MSG_CONTROL" },
- { 0xce, "MSR_PLATFORM_INFO" },
- { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" },
- { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" },
- { 0x1aa, "MSR_MISC_PWR_MGMT" },
- { 0x1ad, "MSR_TURBO_RATIO_LIMIT" },
- { 0x1fc, "MSR_POWER_CTL" },
- };
+ { 0x3a, "IA32_FEATURE_CONTROL" },
+ { 0x13c, "MSR_FEATURE_CONFIG" },
+ { 0x194, "MSR_FLEX_RATIO" },
+ { 0x1a0, "IA32_MISC_ENABLE" },
+ { 0x1a2, "MSR_TEMPERATURE_TARGET" },
+ { 0x199, "IA32_PERF_CTL" },
+ { 0x19b, "IA32_THERM_INTERRUPT" },
+ { 0x401, "IA32_MC0_STATUS" },
+ { 0x2e, "MSR_PIC_MSG_CONTROL" },
+ { 0xce, "MSR_PLATFORM_INFO" },
+ { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" },
+ { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" },
+ { 0x1aa, "MSR_MISC_PWR_MGMT" },
+ { 0x1ad, "MSR_TURBO_RATIO_LIMIT" },
+ { 0x1fc, "MSR_POWER_CTL" },
+};
/*
* The following two tables are the Silvermont registers listed in Table 35-6
@@ -1007,185 +1007,182 @@ int print_intel_core_msrs(void)
* September 2014
* Vol. 3C 35-59
*/
- static const msr_entry_t silvermont_per_core_msrs[] = {
- /*
- * Per core MSRs in Intel Processors Based on the Silvermont Microarchitecture
- * These are MSRs marked as "core"
- *
- */
- { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
- { 0x0010, "IA32_TIME_STAMP_COUNTER" },
- { 0x001b, "IA32_APIC_BASE" },
- { 0x0034, "MSR_SMI_COUNT" },
- { 0x003a, "IA32_FEATURE_CONTROL" },
- { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
- { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
- { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
- { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
- { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
- { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
- { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
- { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
- { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
- { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
- { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
- { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
- { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
- { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
- { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
- { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
- /* Write register
- { 0x0079, "IA32_BIOS_UPDT_TRIG" },
- */
- { 0x008b, "IA32_BIOS_SIGN_ID" },
- { 0x00c1, "IA32_PMC0" },
- { 0x00c2, "IA32_PMC1" },
- { 0x00e7, "IA32_MPERF" },
- { 0x00e8, "IA32_APERF" },
- { 0x00fe, "IA32_MTRRCAP" },
- { 0x0174, "IA32_SYSENTER_CS" },
- { 0x0175, "IA32_SYSENTER_ESP" },
- { 0x0176, "IA32_SYSENTER_EIP" },
- { 0x0179, "IA32_MCG_CAP" },
- { 0x017a, "IA32_MCG_STATUS" },
- { 0x0186, "IA32_PERF_EVNTSEL0" },
- { 0x0187, "IA32_PERF_EVNTSEL1" },
- { 0x0199, "IA32_PERF_CONTROL" },
- { 0x019a, "IA32_CLOCK_MODULATION" },
- { 0x019b, "IA32_THERM_INTERRUPT" },
- { 0x019c, "IA32_THERM_STATUS" },
- { 0x01a0, "IA32_MISC_ENABLES" },
- { 0x01b0, "IA32_ENERGY_PERF_BIAS" },
- { 0x01c9, "MSR_LASTBRANCH_TOS" },
- { 0x01d9, "IA32_DEBUGCTL" },
- { 0x01dd, "MSR_LER_FROM_LIP" },
- { 0x01de, "MSR_LER_TO_LIP" },
- { 0x01f2, "IA32_SMRR_PHYSBASE" },
- { 0x01f3, "IA32_SMRR_PHYSMASK" },
- { 0x0200, "IA32_MTRR_PHYSBASE0" },
- { 0x0201, "IA32_MTRR_PHYSMASK0" },
- { 0x0202, "IA32_MTRR_PHYSBASE1" },
- { 0x0203, "IA32_MTRR_PHYSMASK1" },
- { 0x0204, "IA32_MTRR_PHYSBASE2" },
- { 0x0205, "IA32_MTRR_PHYSMASK2" },
- { 0x0206, "IA32_MTRR_PHYSBASE3" },
- { 0x0207, "IA32_MTRR_PHYSMASK3" },
- { 0x0208, "IA32_MTRR_PHYSBASE4" },
- { 0x0209, "IA32_MTRR_PHYSMASK4" },
- { 0x020a, "IA32_MTRR_PHYSBASE5" },
- { 0x020b, "IA32_MTRR_PHYSMASK5" },
- { 0x020c, "IA32_MTRR_PHYSBASE6" },
- { 0x020d, "IA32_MTRR_PHYSMASK6" },
- { 0x020e, "IA32_MTRR_PHYSBASE7" },
- { 0x020f, "IA32_MTRR_PHYSMASK7" },
- { 0x0250, "IA32_MTRR_FIX64K_00000" },
- { 0x0258, "IA32_MTRR_FIX16K_80000" },
- { 0x0259, "IA32_MTRR_FIX16K_A0000" },
- { 0x0268, "IA32_MTRR_FIX4K_C0000" },
- { 0x0269, "IA32_MTRR_FIX4K_C8000" },
- { 0x026a, "IA32_MTRR_FIX4K_D0000" },
- { 0x026b, "IA32_MTRR_FIX4K_D8000" },
- { 0x026c, "IA32_MTRR_FIX4K_E0000" },
- { 0x026d, "IA32_MTRR_FIX4K_E8000" },
- { 0x026e, "IA32_MTRR_FIX4K_F0000" },
- { 0x026f, "IA32_MTRR_FIX4K_F8000" },
- { 0x0277, "IA32_PAT" },
- { 0x02FF, "IA32_MTRR_DEF_TYPE" },
- { 0x0309, "IA32_FIXED_CTR0" },
- { 0x030a, "IA32_FIXED_CTR1" },
- { 0x030b, "IA32_FIXED_CTR2" },
- { 0x0345, "IA32_PERF_CAPABILITIES" },
- { 0x038d, "IA32_FIXED_CTR_CTRL" },
- { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
- { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
- { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
- { 0x03f1, "MSR_PEBS_ENABLE" },
- { 0x03fd, "MSR_CORE_C6_RESIDENCY" },
- { 0x40c, "IA32_MC3_CTL" },
- { 0x40d, "IA32_MC3_STATUS" },
- { 0x40e, "IA32_MC3_ADDR" },
- { 0x410, "IA32_MC4_CTL" },
- { 0x411, "IA32_MC4_STATUS" },
- { 0x412, "IA32_MC4_ADDR" },
- { 0x0480, "IA32_VMX_BASIC" },
- { 0x0481, "IA32_VMX_PINBASED_CTLS" },
- { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
- { 0x0483, "IA32_VMX_EXIT_CTLS" },
- { 0x0484, "IA32_VMX_ENTRY_CTLS" },
- { 0x0485, "IA32_VMX_MISC" },
- { 0x0486, "IA32_VMX_CR0_FIXED0" },
- { 0x0487, "IA32_VMX_CR0_FIXED1" },
- { 0x0488, "IA32_VMX_CR4_FIXED0" },
- { 0x0489, "IA32_VMX_CR4_FIXED1" },
- { 0x048a, "IA32_VMX_VMCS_ENUM" },
- { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
- { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
- { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
- { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
- { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
- { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
- { 0x0491, "IA32_VMX_FMFUNC" },
- { 0x04c1, "IA32_A_PMC0" },
- { 0x04c2, "IA32_A_PMC1" },
- { 0x0600, "IA32_DS_AREA" },
- { 0x0660, "MSR_CORE_C1_RESIDENCY" },
- { 0x06e0, "IA32_TSC_DEADLINE" },
- };
-
- static const msr_entry_t silvermont_global_msrs[] = {
- /*
- * Common MSRs in Intel Processors Based on the Silvermont Microarchitecture
- * These are MSRs marked as "shared" or "package"
- */
- { 0x0000, "IA32_P5_MC_ADDR" },
- { 0x0001, "IA32_P5_MC_TYPE" },
- { 0x0017, "IA32_PLATFORM_ID" },
- { 0x002a, "MSR_EBC_HARD_POWERON" },
- { 0x00cd, "MSR_FSB_FREQ" },
- { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" },
- { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" },
- { 0x011e, "BBL_CR_CTL3" },
- { 0x0198, "IA32_PERF_STATUS" },
- { 0x01A2, "MSR_TEMPERATURE_TARGET" },
- { 0x01A6, "MSR_OFFCORE_RSP_0" },
- { 0x01A7, "MSR_OFFCORE_RSP_1" },
- { 0x01AD, "MSR_TURBO_RATIO_LIMIT" },
- { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
- { 0x400, "IA32_MC0_CTL" },
- { 0x401, "IA32_MC0_STATUS" },
- { 0x402, "IA32_MC0_ADDR" },
- { 0x404, "IA32_MC1_CTL" },
- { 0x405, "IA32_MC1_STATUS" },
- { 0x408, "IA32_MC2_CTL" },
- { 0x409, "IA32_MC2_STATUS" },
- { 0x40a, "IA32_MC2_ADDR" },
- { 0x414, "MSR_MC5_CTL" },
- { 0x415, "MSR_MC5_STATUS" },
- { 0x416, "MSR_MC5_ADDR" },
- };
+static const msr_entry_t silvermont_per_core_msrs[] = {
+ /*
+ * Per core MSRs in Intel Processors Based on the Silvermont Microarchitecture
+ * These are MSRs marked as "core"
+ *
+ */
+ { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
+ { 0x0010, "IA32_TIME_STAMP_COUNTER" },
+ { 0x001b, "IA32_APIC_BASE" },
+ { 0x0034, "MSR_SMI_COUNT" },
+ { 0x003a, "IA32_FEATURE_CONTROL" },
+ { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
+ { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
+ { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
+ { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
+ { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
+ { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
+ { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
+ { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
+ { 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
+ { 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
+ { 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
+ { 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
+ { 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
+ { 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
+ { 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
+ { 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
+ /* Write register
+ { 0x0079, "IA32_BIOS_UPDT_TRIG" },
+ */
+ { 0x008b, "IA32_BIOS_SIGN_ID" },
+ { 0x00c1, "IA32_PMC0" },
+ { 0x00c2, "IA32_PMC1" },
+ { 0x00e7, "IA32_MPERF" },
+ { 0x00e8, "IA32_APERF" },
+ { 0x00fe, "IA32_MTRRCAP" },
+ { 0x0174, "IA32_SYSENTER_CS" },
+ { 0x0175, "IA32_SYSENTER_ESP" },
+ { 0x0176, "IA32_SYSENTER_EIP" },
+ { 0x0179, "IA32_MCG_CAP" },
+ { 0x017a, "IA32_MCG_STATUS" },
+ { 0x0186, "IA32_PERF_EVNTSEL0" },
+ { 0x0187, "IA32_PERF_EVNTSEL1" },
+ { 0x0199, "IA32_PERF_CONTROL" },
+ { 0x019a, "IA32_CLOCK_MODULATION" },
+ { 0x019b, "IA32_THERM_INTERRUPT" },
+ { 0x019c, "IA32_THERM_STATUS" },
+ { 0x01a0, "IA32_MISC_ENABLES" },
+ { 0x01b0, "IA32_ENERGY_PERF_BIAS" },
+ { 0x01c9, "MSR_LASTBRANCH_TOS" },
+ { 0x01d9, "IA32_DEBUGCTL" },
+ { 0x01dd, "MSR_LER_FROM_LIP" },
+ { 0x01de, "MSR_LER_TO_LIP" },
+ { 0x01f2, "IA32_SMRR_PHYSBASE" },
+ { 0x01f3, "IA32_SMRR_PHYSMASK" },
+ { 0x0200, "IA32_MTRR_PHYSBASE0" },
+ { 0x0201, "IA32_MTRR_PHYSMASK0" },
+ { 0x0202, "IA32_MTRR_PHYSBASE1" },
+ { 0x0203, "IA32_MTRR_PHYSMASK1" },
+ { 0x0204, "IA32_MTRR_PHYSBASE2" },
+ { 0x0205, "IA32_MTRR_PHYSMASK2" },
+ { 0x0206, "IA32_MTRR_PHYSBASE3" },
+ { 0x0207, "IA32_MTRR_PHYSMASK3" },
+ { 0x0208, "IA32_MTRR_PHYSBASE4" },
+ { 0x0209, "IA32_MTRR_PHYSMASK4" },
+ { 0x020a, "IA32_MTRR_PHYSBASE5" },
+ { 0x020b, "IA32_MTRR_PHYSMASK5" },
+ { 0x020c, "IA32_MTRR_PHYSBASE6" },
+ { 0x020d, "IA32_MTRR_PHYSMASK6" },
+ { 0x020e, "IA32_MTRR_PHYSBASE7" },
+ { 0x020f, "IA32_MTRR_PHYSMASK7" },
+ { 0x0250, "IA32_MTRR_FIX64K_00000" },
+ { 0x0258, "IA32_MTRR_FIX16K_80000" },
+ { 0x0259, "IA32_MTRR_FIX16K_A0000" },
+ { 0x0268, "IA32_MTRR_FIX4K_C0000" },
+ { 0x0269, "IA32_MTRR_FIX4K_C8000" },
+ { 0x026a, "IA32_MTRR_FIX4K_D0000" },
+ { 0x026b, "IA32_MTRR_FIX4K_D8000" },
+ { 0x026c, "IA32_MTRR_FIX4K_E0000" },
+ { 0x026d, "IA32_MTRR_FIX4K_E8000" },
+ { 0x026e, "IA32_MTRR_FIX4K_F0000" },
+ { 0x026f, "IA32_MTRR_FIX4K_F8000" },
+ { 0x0277, "IA32_PAT" },
+ { 0x02FF, "IA32_MTRR_DEF_TYPE" },
+ { 0x0309, "IA32_FIXED_CTR0" },
+ { 0x030a, "IA32_FIXED_CTR1" },
+ { 0x030b, "IA32_FIXED_CTR2" },
+ { 0x0345, "IA32_PERF_CAPABILITIES" },
+ { 0x038d, "IA32_FIXED_CTR_CTRL" },
+ { 0x038e, "IA32_PERF_GLOBAL_STATUS" },
+ { 0x038f, "IA32_PERF_GLOBAL_CTRL" },
+ { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
+ { 0x03f1, "MSR_PEBS_ENABLE" },
+ { 0x03fd, "MSR_CORE_C6_RESIDENCY" },
+ { 0x40c, "IA32_MC3_CTL" },
+ { 0x40d, "IA32_MC3_STATUS" },
+ { 0x40e, "IA32_MC3_ADDR" },
+ { 0x410, "IA32_MC4_CTL" },
+ { 0x411, "IA32_MC4_STATUS" },
+ { 0x412, "IA32_MC4_ADDR" },
+ { 0x0480, "IA32_VMX_BASIC" },
+ { 0x0481, "IA32_VMX_PINBASED_CTLS" },
+ { 0x0482, "IA32_VMX_PROCBASED_CTLS" },
+ { 0x0483, "IA32_VMX_EXIT_CTLS" },
+ { 0x0484, "IA32_VMX_ENTRY_CTLS" },
+ { 0x0485, "IA32_VMX_MISC" },
+ { 0x0486, "IA32_VMX_CR0_FIXED0" },
+ { 0x0487, "IA32_VMX_CR0_FIXED1" },
+ { 0x0488, "IA32_VMX_CR4_FIXED0" },
+ { 0x0489, "IA32_VMX_CR4_FIXED1" },
+ { 0x048a, "IA32_VMX_VMCS_ENUM" },
+ { 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
+ { 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
+ { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
+ { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
+ { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
+ { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
+ { 0x0491, "IA32_VMX_FMFUNC" },
+ { 0x04c1, "IA32_A_PMC0" },
+ { 0x04c2, "IA32_A_PMC1" },
+ { 0x0600, "IA32_DS_AREA" },
+ { 0x0660, "MSR_CORE_C1_RESIDENCY" },
+ { 0x06e0, "IA32_TSC_DEADLINE" },
+};
- typedef struct {
- unsigned int model;
- const msr_entry_t *global_msrs;
- unsigned int num_global_msrs;
- const msr_entry_t *per_core_msrs;
- unsigned int num_per_core_msrs;
- } cpu_t;
+static const msr_entry_t silvermont_global_msrs[] = {
+ /*
+ * Common MSRs in Intel Processors Based on the Silvermont Microarchitecture
+ * These are MSRs marked as "shared" or "package"
+ */
+ { 0x0000, "IA32_P5_MC_ADDR" },
+ { 0x0001, "IA32_P5_MC_TYPE" },
+ { 0x0017, "IA32_PLATFORM_ID" },
+ { 0x002a, "MSR_EBC_HARD_POWERON" },
+ { 0x00cd, "MSR_FSB_FREQ" },
+ { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" },
+ { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" },
+ { 0x011e, "BBL_CR_CTL3" },
+ { 0x0198, "IA32_PERF_STATUS" },
+ { 0x01A2, "MSR_TEMPERATURE_TARGET" },
+ { 0x01A6, "MSR_OFFCORE_RSP_0" },
+ { 0x01A7, "MSR_OFFCORE_RSP_1" },
+ { 0x01AD, "MSR_TURBO_RATIO_LIMIT" },
+ { 0x03fa, "MSR_PKG_C6_RESIDENCY" },
+ { 0x400, "IA32_MC0_CTL" },
+ { 0x401, "IA32_MC0_STATUS" },
+ { 0x402, "IA32_MC0_ADDR" },
+ { 0x404, "IA32_MC1_CTL" },
+ { 0x405, "IA32_MC1_STATUS" },
+ { 0x408, "IA32_MC2_CTL" },
+ { 0x409, "IA32_MC2_STATUS" },
+ { 0x40a, "IA32_MC2_ADDR" },
+ { 0x414, "MSR_MC5_CTL" },
+ { 0x415, "MSR_MC5_STATUS" },
+ { 0x416, "MSR_MC5_ADDR" },
+};
- cpu_t cpulist[] = {
- { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 },
- { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
- { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
- { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
- { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
- { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
- { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
- { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
+typedef struct {
+ unsigned int model;
+ const msr_entry_t *global_msrs;
+ unsigned int num_global_msrs;
+ const msr_entry_t *per_core_msrs;
+ unsigned int num_per_core_msrs;
+} cpu_t;
+cpu_t cpulist[] = {
+ { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 },
+ { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
+ { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
+ { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
+ { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) },
+ { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
+ { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
+ { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
{ CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */
-
};
-
cpu_t *cpu = NULL;
/* Get CPU family and model, not the stepping
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index c6f486f..5931cb0 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -44,9 +44,9 @@ static inline uint8_t inb(unsigned port)
}
static inline uint16_t inw(unsigned port)
{
- uint16_t data;
- __asm volatile("inw %w1,%0": "=a" (data) : "d" (port));
- return data;
+ uint16_t data;
+ __asm volatile("inw %w1,%0": "=a" (data) : "d" (port));
+ return data;
}
static inline uint32_t inl(unsigned port)
{
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index de70e6d..67b0e19 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -123,51 +123,51 @@ static const io_register_t sandybridge_dmi_registers[] = {
* 329002-002
*/
static const io_register_t haswell_ult_dmi_registers[] = {
- { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
- { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
- { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
- { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
-/* { 0x0E, 2, "RSVD" }, // Reserved */
- { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
- { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
-/* { 0x18, 2, "RSVD" }, // Reserved */
- { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
- { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
- { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
-/* { 0x24, 2, "RSVD" }, // Reserved */
- { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
- { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability
- { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control
-/* { 0x30, 2, "RSVD" }, // Reserved */
- { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status
- { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
- { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
-/* { 0x3C, 2, "RSVD" }, // Reserved */
- { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
- { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */
- { 0x44, 4, "DMIESD" }, // DMI Element Self Description
-/* { 0x48, 4, "RSVD" }, // Reserved */
-/* { 0x4C, 4, "RSVD" }, // Reserved */
- { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
-/* { 0x54, 4, "RSVD" }, // Reserved */
- { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
- { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
- { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
-/* { 0x64, 4, "RSVD" }, // Reserved */
- { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
-/* { 0x6C, 4, "RSVD" }, // Reserved */
-/* { 0x70, 4, "RSVD" }, // Reserved */
-/* { 0x74, 4, "RSVD" }, // Reserved */
-/* { 0x78, 4, "RSVD" }, // Reserved */
-/* { 0x7C, 4, "RSVD" }, // Reserved */
-/* { 0x80, 4, "RSVD" }, // Reserved */
-/* { 0x84, 4, "RSVD" }, // Reserved */
- { 0x88, 2, "LCTL" }, // Link Control
- /* ... - Reserved */
- { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status
- { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask
- { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status
- { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
+ { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
+ { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
+ { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
+ { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control
+/* { 0x0E, 2, "RSVD" }, // Reserved */
+ { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
+ { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
+/* { 0x18, 2, "RSVD" }, // Reserved */
+ { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
+ { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
+ { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
+/* { 0x24, 2, "RSVD" }, // Reserved */
+ { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
+ { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability
+ { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control
+/* { 0x30, 2, "RSVD" }, // Reserved */
+ { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status
+ { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
+ { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
+/* { 0x3C, 2, "RSVD" }, // Reserved */
+ { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
+ { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */
+ { 0x44, 4, "DMIESD" }, // DMI Element Self Description
+/* { 0x48, 4, "RSVD" }, // Reserved */
+/* { 0x4C, 4, "RSVD" }, // Reserved */
+ { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
+/* { 0x54, 4, "RSVD" }, // Reserved */
+ { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
+ { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
+ { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
+/* { 0x64, 4, "RSVD" }, // Reserved */
+ { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
+/* { 0x6C, 4, "RSVD" }, // Reserved */
+/* { 0x70, 4, "RSVD" }, // Reserved */
+/* { 0x74, 4, "RSVD" }, // Reserved */
+/* { 0x78, 4, "RSVD" }, // Reserved */
+/* { 0x7C, 4, "RSVD" }, // Reserved */
+/* { 0x80, 4, "RSVD" }, // Reserved */
+/* { 0x84, 4, "RSVD" }, // Reserved */
+ { 0x88, 2, "LCTL" }, // Link Control
+ /* ... - Reserved */
+ { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status
+ { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask
+ { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status
+ { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
/* ... - Reserved */
};
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