[coreboot-gerrit] New patch to review for coreboot: mainboard/iwill: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Fri Oct 7 18:21:02 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16928
-gerrit
commit 79069dd71bb0a492f8a7835e27f0a9307d7d924e
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Fri Oct 7 18:19:20 2016 +0200
mainboard/iwill: Use C89 comments style & remove commented code
Change-Id: I5bea94bbb5596468004d96749cd6ea46eed19f65
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/iwill/dk8_htx/acpi_tables.c | 18 +++++-----
src/mainboard/iwill/dk8_htx/fadt.c | 14 ++++----
src/mainboard/iwill/dk8_htx/get_bus_conf.c | 46 ++++++++++---------------
src/mainboard/iwill/dk8_htx/mptable.c | 54 +++++++++++++++---------------
src/mainboard/iwill/dk8_htx/resourcemap.c | 2 +-
src/mainboard/iwill/dk8_htx/romstage.c | 30 ++++++-----------
6 files changed, 73 insertions(+), 91 deletions(-)
diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c
index b9e8468..0e72047 100644
--- a/src/mainboard/iwill/dk8_htx/acpi_tables.c
+++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c
@@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current)
for(i = 1; i< sysconf.hc_possible_num; i++) {
unsigned d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
- // 8131 need to use +4
+ /* 8131 need to use +4 */
switch (sysconf.hcid[i]) {
case 1:
@@ -136,15 +136,15 @@ unsigned long mainboard_write_acpi_tables(device_t device,
int i;
- get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
+ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16byte */
start = ALIGN(start, 16);
current = start;
- //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
+ /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
- for(i = 1; i < sysconf.hc_possible_num; i++) { // 0: is hc sblink
+ for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
const char *file_name;
if((sysconf.pci1234[i] & 1) != 1 ) continue;
uint8_t c;
@@ -154,21 +154,21 @@ unsigned long mainboard_write_acpi_tables(device_t device,
else {
c = (uint8_t) ('A' + i - 1 - 6);
}
- printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */
current = ALIGN(current, 8);
ssdtx = (acpi_header_t *)current;
switch(sysconf.hcid[i]) {
- case 1: //8132
+ case 1: /* 8132 */
file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml";
break;
- case 2: //8151
+ case 2: /* 8151 */
file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml";
break;
- case 3: //8131
+ case 3: /* 8131 */
file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml";
break;
default:
- //HTX no io apic
+ /* HTX no io apic */
file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml";
break;
}
diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c
index 5a7c2a7..02edb6c 100644
--- a/src/mainboard/iwill/dk8_htx/fadt.c
+++ b/src/mainboard/iwill/dk8_htx/fadt.c
@@ -27,11 +27,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
- // 3=Workstation, 4=Enterprise Server, 7=Performance Server
+ /* 3=Workstation, 4=Enterprise Server, 7=Performance Server */
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
- // disable system management mode by setting to 0:
- fadt->smi_cmd = 0;//pm_base+0x2f;
+ /* disable system management mode by setting to 0: */
+ fadt->smi_cmd = 0;
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
@@ -61,10 +61,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
- fadt->day_alrm = 0; // 0x7d these have to be
- fadt->mon_alrm = 0; // 0x7e added to cmos.layout
- fadt->century = 0; // 0x7f to make rtc alrm work
- fadt->iapc_boot_arch = 0x3; // See table 5-11
+ fadt->day_alrm = 0; /* 0x7d these have to be */
+ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
+ fadt->century = 0; /* 0x7f to make rtc alrm work */
+ fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
fadt->flags = 0x25;
fadt->res2 = 0;
diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
index 25dcab1..b87b340 100644
--- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c
+++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
@@ -10,30 +10,20 @@
#include <stdlib.h>
#include "mb_sysconf.h"
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
struct mb_sysconf_t mb_sysconf;
-static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0, // SB chain m
- 0x0000000, // HTX
- 0x0000100, // co processor on socket 1
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
+static unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */
+ /*You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */
+ 0x0000ff0, /* SB chain m */
+ 0x0000000, /* HTX */
+ 0x0000100, /* co processor on socket 1 */
};
-static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+static unsigned hcdnx[] = { /*HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */
0x20202020,
0x20202020,
0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
};
static unsigned get_bus_conf_done = 0;
@@ -51,20 +41,20 @@ static unsigned get_hcid(unsigned i)
dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
switch (dev->device) {
- case 0x7458: //8132
+ case 0x7458: /* 8132 */
id = 1;
break;
- case 0x7454: //8151
+ case 0x7454: /* 8151 */
id = 2;
break;
- case 0x7450: //8131
+ case 0x7450: /* 8131 */
id = 3;
break;
}
- // we may need more way to find out hcid: subsystem id? GPIO read ?
+ /* we may need more way to find out hcid: subsystem id? GPIO read ? */
- // we need use id for 1. bus num, 2. mptable, 3. ACPI table
+ /* we need use id for 1. bus num, 2. mptable, 3. ACPI table */
return id;
}
@@ -79,7 +69,7 @@ void get_bus_conf(void)
struct mb_sysconf_t *m;
if (get_bus_conf_done == 1)
- return; //do it only once
+ return; /* do it only once */
get_bus_conf_done = 1;
@@ -137,13 +127,13 @@ void get_bus_conf(void)
if (!(sysconf.pci1234[i] & 0x1))
continue;
- // check hcid type here
+ /* check hcid type here */
sysconf.hcid[i] = get_hcid(i);
switch (sysconf.hcid[i]) {
- case 1: //8132
- case 3: //8131
+ case 1: /* 8132 */
+ case 3: /* 8131 */
m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
@@ -177,7 +167,7 @@ void get_bus_conf(void)
break;
- case 2: //8151
+ case 2: /* 8151 */
m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
@@ -201,7 +191,7 @@ void get_bus_conf(void)
j++;
}
-/*I/O APICs: APIC ID Version State Address*/
+/* I/O APICs: APIC ID Version State Address*/
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
apicid_base = get_apicid_base(3);
else
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index b1fcdd1..cca131f 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); //8111
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, VIO_APIC_VADDR); /* 8111 */
{
device_t dev;
struct resource *res;
@@ -56,8 +56,8 @@ static void *smp_write_config_table(void *v)
if(!(sysconf.pci1234[i] & 0x1) ) continue;
switch(sysconf.hcid[i]) {
- case 1: // 8132
- case 3: // 8131
+ case 1: /* 8132 */
+ case 3: /* 8131 */
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -83,47 +83,47 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
-//??? What
+/*??? What */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
-// Onboard AMD USB
+/* Onboard AMD USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
-// Onboard VGA
+/* Onboard VGA */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6 << 2)|0, m->apicid_8111, 0x12);
-//Slot 5 PCI 32
+/* Slot 5 PCI 32 */
for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); /* 16 */
}
-//Slot 6 PCI 32
+/* Slot 6 PCI 32 */
for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); /* 16 */
}
-//Slot 1: HTX
+/* Slot 1: HTX */
-//Slot 2 PCI-X 133/100/66
+/* Slot 2 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2 << 2)|i, m->apicid_8132_2, (2+i)%4); //30
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2 << 2)|i, m->apicid_8132_2, (2+i)%4); /* 30 */
}
-//Slot 3 PCI-X 133/100/66
+/* Slot 3 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); /* 25 */
}
-//Slot 4 PCI-X 133/100/66
+/* Slot 4 PCI-X 133/100/66 */
for(i = 0; i < 4; i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2 << 2)|i, m->apicid_8132_1, (2+i)%4); //26
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2 << 2)|i, m->apicid_8132_1, (2+i)%4); /* 26 */
}
-//Onboard NICS
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3 << 2)|0, m->apicid_8132_1, 3); //27
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4 << 2)|0, m->apicid_8132_1, 0); //24
+/* Onboard NICS */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3 << 2)|0, m->apicid_8132_1, 3); /* 27 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4 << 2)|0, m->apicid_8132_1, 0); /* 24 */
-//Onboard SATA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5 << 2)|0, m->apicid_8132_1, 1); //25
+/* Onboard SATA */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5 << 2)|0, m->apicid_8132_1, 1); /* 25 */
j = 0;
@@ -139,9 +139,9 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- //Slot 1 PCI-X 133/100/66
+ /* Slot 1 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4);
}
}
}
@@ -150,9 +150,9 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- //Slot 2 PCI-X 133/100/66
+ /* Slot 2 PCI-X 133/100/66 */
for(ii = 0; ii < 4; ii++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); /* 25 */
}
}
}
@@ -160,7 +160,7 @@ static void *smp_write_config_table(void *v)
break;
case 2:
- // Slot AGP
+ /* Slot AGP */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
break;
}
diff --git a/src/mainboard/iwill/dk8_htx/resourcemap.c b/src/mainboard/iwill/dk8_htx/resourcemap.c
index 11e80ea..9950562 100644
--- a/src/mainboard/iwill/dk8_htx/resourcemap.c
+++ b/src/mainboard/iwill/dk8_htx/resourcemap.c
@@ -251,7 +251,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, /* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index c1c141e..20ecb7c 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -68,10 +68,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // first node
+ /* first node */
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
- // second node
+ /* second node */
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
@@ -95,11 +95,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
- setup_coherent_ht_domain(); // routing table and start other core0
+ setup_coherent_ht_domain(); /* routing table and start other core0 */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
+ /* It is said that we should start core1 after all core0 launched */
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
@@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
/* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+ ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
#if CONFIG_SET_FIDVID
{
@@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
+ /* show final fid and vid */
{
msr_t msr;
msr = rdmsr(0xc0010042);
@@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
+ /* fidvid change will issue one LDTSTOP and the HT change will be effective too */
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
@@ -139,25 +139,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now;
+ /* It's the time to set ctrl in sysinfo now; */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
-#if 0
- dump_smbus_registers();
-#endif
-
memreset_setup();
- //do we need apci timer, tsc...., only debug need it for better output
+ /* do we need apci timer, tsc...., only debug need it for better output */
/* all ap stopped? */
- init_timer(); // Need to use TMICT to synchronize FID/VID
+ init_timer(); /* Need to use TMICT to synchronize FID/VID */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-#if 0
- dump_pci_devices();
-#endif
-
- post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
+ post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */
}
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