[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: Disable HECI2 device reset on S3 resume

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16870

-gerrit

commit 2c57dd183fe1ed3fe0468ed7b0867bec3f6efb95
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Mon Oct 3 16:05:20 2016 -0700

    soc/intel/apollolake: Disable HECI2 device reset on S3 resume
    
    CSE has a secure variable storage feature. However, this storage is
    expected to be reset during S3 resume flow. Since coreboot does not
    use secure storage feature, disable HECI2 reset request. This saves
    appr 130ms of resume time.
    
    BUG=chrome-os-partner:56941
    BRANCH=none
    TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note
    FspMemoryInit time is not significantly different from normal boot
    time case.
    
    Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/romstage.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index b9733de..7900b11 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -169,6 +169,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
 	 */
 	mupd->FspmConfig.SkipCseRbp =
 		IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED);
+
+	mupd->FspmConfig.EnableS3Heci2 = 0;
 }
 
 __attribute__ ((weak))