[coreboot-gerrit] New patch to review for coreboot: buildsystem: Promote rules.h to default include
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Nov 30 14:39:27 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17656
-gerrit
commit e67bd0b9772940bbca064032f955885cc597fce1
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Nov 30 14:53:24 2016 +0200
buildsystem: Promote rules.h to default include
Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
Makefile.inc | 1 +
src/arch/arm/armv7/cpu.S | 1 -
src/arch/arm64/boot.c | 1 -
src/arch/arm64/include/arch/header.ld | 1 -
src/arch/riscv/boot.c | 1 -
src/arch/x86/acpi_s3.c | 1 -
src/arch/x86/assembly_entry.S | 1 -
src/arch/x86/include/arch/acpi.h | 1 -
src/arch/x86/include/arch/cpu.h | 1 -
src/arch/x86/include/arch/early_variables.h | 1 -
src/arch/x86/include/arch/header.ld | 1 -
src/arch/x86/include/arch/io.h | 1 -
src/arch/x86/include/arch/memlayout.h | 1 -
src/console/console.c | 1 -
src/console/init.c | 1 -
src/console/post.c | 1 -
src/cpu/intel/microcode/microcode.c | 1 -
src/cpu/x86/32bit/entry32.inc | 1 -
src/drivers/intel/fsp1_1/cache_as_ram.inc | 1 -
src/drivers/intel/fsp1_1/include/fsp/util.h | 1 -
src/drivers/intel/fsp2_0/include/fsp/info_header.h | 1 -
src/drivers/spi/spi_flash.c | 1 -
src/drivers/uart/uart8250io.c | 1 -
src/drivers/uart/uart8250mem.c | 1 -
src/include/bootstate.h | 1 -
src/include/cbmem.h | 1 -
src/include/console/cbmem_console.h | 1 -
src/include/console/console.h | 1 -
src/include/console/ne2k.h | 1 -
src/include/console/qemu_debugcon.h | 1 -
src/include/console/spi.h | 1 -
src/include/console/spkmodem.h | 1 -
src/include/console/uart.h | 1 -
src/include/console/usb.h | 1 -
src/include/device/device.h | 1 -
src/include/device/pci.h | 1 -
src/include/device/pnp.h | 1 -
src/include/memlayout.h | 1 -
src/lib/bootmode.c | 1 -
src/lib/cbmem_common.c | 1 -
src/lib/ext_stage_cache.c | 1 -
src/lib/imd_cbmem.c | 1 -
src/lib/prog_loaders.c | 1 -
src/lib/timestamp.c | 1 -
src/mainboard/google/chell/chromeos.c | 1 -
src/mainboard/google/cyan/chromeos.c | 1 -
src/mainboard/google/eve/chromeos.c | 1 -
src/mainboard/google/glados/chromeos.c | 1 -
src/mainboard/google/lars/chromeos.c | 1 -
src/mainboard/google/reef/ec.c | 1 -
src/mainboard/google/storm/mmu.c | 1 -
src/mainboard/intel/kblrvp/chromeos.c | 1 -
src/mainboard/intel/kunimitsu/chromeos.c | 1 -
src/mainboard/intel/strago/chromeos.c | 1 -
src/northbridge/intel/fsp_rangeley/northbridge.h | 1 -
src/northbridge/intel/gm45/gm45.h | 1 -
src/northbridge/intel/sandybridge/sandybridge.h | 1 -
src/soc/intel/apollolake/include/soc/pci_devs.h | 1 -
src/soc/intel/apollolake/p2sb.c | 1 -
src/soc/intel/apollolake/pmutil.c | 1 -
src/soc/intel/braswell/acpi.c | 1 -
src/soc/intel/braswell/include/soc/iosf.h | 1 -
src/soc/intel/braswell/include/soc/nvs.h | 1 -
src/soc/intel/braswell/include/soc/smm.h | 1 -
src/soc/intel/braswell/pmutil.c | 1 -
src/soc/intel/braswell/spi.c | 1 -
src/soc/intel/braswell/tsc_freq.c | 1 -
src/soc/intel/quark/romstage/car_stage_entry.S | 1 -
src/soc/intel/skylake/bootblock/cache_as_ram.S | 1 -
src/soc/intel/skylake/include/soc/flash_controller.h | 1 -
src/soc/intel/skylake/include/soc/nvs.h | 1 -
src/soc/intel/skylake/include/soc/pch.h | 1 -
src/soc/intel/skylake/include/soc/pci_devs.h | 1 -
src/soc/intel/skylake/include/soc/xhci.h | 1 -
src/soc/intel/skylake/pmutil.c | 1 -
src/soc/intel/skylake/romstage/car_stage.S | 1 -
src/soc/marvell/mvmap2315/uart.c | 1 -
src/soc/nvidia/tegra210/include/soc/memlayout.ld | 1 -
src/vboot/bootmode.c | 1 -
src/vboot/vboot_common.c | 1 -
src/vboot/vboot_loader.c | 1 -
src/vendorcode/google/chromeos/chromeos.h | 1 -
82 files changed, 1 insertion(+), 81 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index a193158..5f00244 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -351,6 +351,7 @@ CPPFLAGS_common += -Isrc/device/oprom/include
VBOOT_SOURCE ?= 3rdparty/vboot
CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
CPPFLAGS_common += -include $(src)/include/kconfig.h
+CPPFLAGS_common += -include $(src)/include/rules.h
CPPFLAGS_common += -I3rdparty
CFLAGS_common += -pipe -g -nostdinc
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
index 21a16d2..b1ab048 100644
--- a/src/arch/arm/armv7/cpu.S
+++ b/src/arch/arm/armv7/cpu.S
@@ -31,7 +31,6 @@
*/
#include <arch/asm.h>
-#include <rules.h>
/*
* Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0]
diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
index d498cd9..7909d5f 100644
--- a/src/arch/arm64/boot.c
+++ b/src/arch/arm64/boot.c
@@ -21,7 +21,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <program_loading.h>
-#include <rules.h>
#include <string.h>
static void run_payload(struct prog *prog)
diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld
index c82cb3f..f610ec0 100644
--- a/src/arch/arm64/include/arch/header.ld
+++ b/src/arch/arm64/include/arch/header.ld
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index 9483c48..0fbfdbc 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -16,7 +16,6 @@
#include <program_loading.h>
#include <vm.h>
#include <arch/encoding.h>
-#include <rules.h>
#include <console/console.h>
#include <commonlib/configstring.h>
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index ffec64d..fcaeba6 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -21,7 +21,6 @@
#include <timestamp.h>
#include <program_loading.h>
#include <romstage_handoff.h>
-#include <rules.h>
#include <symbols.h>
#if ENV_RAMSTAGE
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index d1f5d61..e530745 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
/*
*Take the path where CAR_GLOBAL variables just need to be cleared when
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 7c29648..1765ac0 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -44,7 +44,6 @@
#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
#include <stdint.h>
-#include <rules.h>
#include <commonlib/helpers.h>
#include <device/device.h>
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index faa2375..013a73d 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -16,7 +16,6 @@
#include <stdint.h>
#include <stddef.h>
-#include <rules.h>
/*
* EFLAGS bits
diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h
index e78b846..fe32fab 100644
--- a/src/arch/x86/include/arch/early_variables.h
+++ b/src/arch/x86/include/arch/early_variables.h
@@ -18,7 +18,6 @@
#include <arch/symbols.h>
#include <stdlib.h>
-#include <rules.h>
#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM)
asm(".section .car.global_data,\"w\", at nobits");
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld
index 77eb187..3bf98fe 100644
--- a/src/arch/x86/include/arch/header.ld
+++ b/src/arch/x86/include/arch/header.ld
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
PHDRS
{
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 69922e2..fa91ea5 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -16,7 +16,6 @@
#include <endian.h>
#include <stdint.h>
-#include <rules.h>
/* FIXME: Sources for romstage still use device_t. */
/* Use pci_devfn_t or pnp_devfn_t instead */
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 83e5b90..f93dece 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -16,7 +16,6 @@
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
-#include <rules.h>
#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
/* No .data or .bss sections. Cache as RAM is handled separately. */
diff --git a/src/console/console.c b/src/console/console.c
index 7b0dfc2..dbe503d 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -21,7 +21,6 @@
#include <console/uart.h>
#include <console/usb.h>
#include <console/spi.h>
-#include <rules.h>
void console_hw_init(void)
{
diff --git a/src/console/init.c b/src/console/init.c
index 189079b..e4d0e6c 100644
--- a/src/console/init.c
+++ b/src/console/init.c
@@ -19,7 +19,6 @@
#include <console/streams.h>
#include <device/pci.h>
#include <option.h>
-#include <rules.h>
#include <version.h>
/* While in romstage, console loglevel is built-time constant. */
diff --git a/src/console/post.c b/src/console/post.c
index 481a1f4..08cf640 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
-#include <rules.h>
/* Write POST information */
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 1285c12..f3ea6cb 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -27,7 +27,6 @@
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
-#include <rules.h>
#if !defined(__PRE_RAM__)
#include <smp/spinlock.h>
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 8c39008..133f708 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -2,7 +2,6 @@
#include <arch/rom_segs.h>
#include <cpu/x86/post_code.h>
-#include <rules.h>
.code32
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index 6611fa1..0302cc6 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -24,7 +24,6 @@
* performs the final stage of initialization.
*/
-#include <rules.h>
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
index eea0c33..c243f97 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/util.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -17,7 +17,6 @@
#ifndef FSP1_1_UTIL_H
#define FSP1_1_UTIL_H
-#include <rules.h>
#include <fsp/api.h>
/* Current users expect to get the SoC's FSP definitions by including util.h. */
#include <fsp/soc_binding.h>
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index 6351b32..2fb08cd 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -13,7 +13,6 @@
#ifndef _FSP2_0_INFO_HEADER_H_
#define _FSP2_0_INFO_HEADER_H_
-#include <rules.h>
#include <stdint.h>
#include <stdlib.h>
#include <types.h>
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index b2fdab9..cb85425 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -13,7 +13,6 @@
#include <cbfs.h>
#include <cpu/x86/smm.h>
#include <delay.h>
-#include <rules.h>
#include <stdlib.h>
#include <string.h>
#include <spi-generic.h>
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index ac3315a..b8edd0c 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
#include <stdlib.h>
#include <arch/io.h>
#include <console/uart.h>
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 4e53a92..7e1a12a 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -19,7 +19,6 @@
#include <console/uart.h>
#include <device/device.h>
#include <delay.h>
-#include <rules.h>
#include <stdint.h>
#include "uart8250reg.h"
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 09178a5..49f8c2a 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -15,7 +15,6 @@
#ifndef BOOTSTATE_H
#define BOOTSTATE_H
-#include <rules.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 5c4b7c7..87b63d8 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -18,7 +18,6 @@
#define _CBMEM_H_
#include <commonlib/cbmem_id.h>
-#include <rules.h>
#include <stddef.h>
#include <stdint.h>
#include <boot/coreboot_tables.h>
diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h
index de1144b..04b6b38 100644
--- a/src/include/console/cbmem_console.h
+++ b/src/include/console/cbmem_console.h
@@ -15,7 +15,6 @@
#ifndef _CONSOLE_CBMEM_CONSOLE_H_
#define _CONSOLE_CBMEM_CONSOLE_H_
-#include <rules.h>
#include <stdint.h>
void cbmemc_init(void);
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 013ef20..0c66b19 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -17,7 +17,6 @@
#define CONSOLE_CONSOLE_H_
#include <stdint.h>
-#include <rules.h>
#include <arch/cpu.h>
#include <console/post_codes.h>
#include <commonlib/loglevel.h>
diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h
index d7974b5..c79d58c 100644
--- a/src/include/console/ne2k.h
+++ b/src/include/console/ne2k.h
@@ -16,7 +16,6 @@
#ifndef _NE2K_H__
#define _NE2K_H__
-#include <rules.h>
#include <stdint.h>
void ne2k_append_data(unsigned char *d, int len, unsigned int base);
diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h
index 257ae58..33b274a 100644
--- a/src/include/console/qemu_debugcon.h
+++ b/src/include/console/qemu_debugcon.h
@@ -1,7 +1,6 @@
#ifndef _QEMU_DEBUGCON_H_
#define _QEMU_DEBUGCON_H_
-#include <rules.h>
#include <stdint.h>
void qemu_debugcon_init(void);
diff --git a/src/include/console/spi.h b/src/include/console/spi.h
index bf58a36..451359c 100644
--- a/src/include/console/spi.h
+++ b/src/include/console/spi.h
@@ -16,7 +16,6 @@
#ifndef CONSOLE_SPI_H
#define CONSOLE_SPI_H 1
-#include <rules.h>
#include <stdint.h>
void spiconsole_init(void);
diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h
index dfd21d4..76760fd 100644
--- a/src/include/console/spkmodem.h
+++ b/src/include/console/spkmodem.h
@@ -1,7 +1,6 @@
#ifndef SPKMODEM_H
#define SPKMODEM_H 1
-#include <rules.h>
#include <stdint.h>
void spkmodem_init(void);
diff --git a/src/include/console/uart.h b/src/include/console/uart.h
index ffcc088..da82d99 100644
--- a/src/include/console/uart.h
+++ b/src/include/console/uart.h
@@ -16,7 +16,6 @@
#ifndef CONSOLE_UART_H
#define CONSOLE_UART_H
-#include <rules.h>
#include <stdint.h>
/* Return the clock frequency UART uses as reference clock for
diff --git a/src/include/console/usb.h b/src/include/console/usb.h
index b758c03..7f5998d 100644
--- a/src/include/console/usb.h
+++ b/src/include/console/usb.h
@@ -17,7 +17,6 @@
#ifndef _CONSOLE_USB_H_
#define _CONSOLE_USB_H_
-#include <rules.h>
#include <stdint.h>
int usbdebug_init(void);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 95fabf4..ada985b 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -10,7 +10,6 @@
#include <stdint.h>
#include <stddef.h>
-#include <rules.h>
#include <device/resource.h>
#include <device/path.h>
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index e167752..1e8adad 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <stddef.h>
-#include <rules.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/resource.h>
diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h
index cfed7c7..d84541f 100644
--- a/src/include/device/pnp.h
+++ b/src/include/device/pnp.h
@@ -2,7 +2,6 @@
#define DEVICE_PNP_H
#include <stdint.h>
-#include <rules.h>
#include <device/device.h>
#include <device/pnp_def.h>
#include <arch/io.h>
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index a68b21f..4d44be0 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -18,7 +18,6 @@
#ifndef __MEMLAYOUT_H
#define __MEMLAYOUT_H
-#include <rules.h>
#include <arch/memlayout.h>
/* Macros that the architecture can override. */
diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c
index dcee2d1..29682eb 100644
--- a/src/lib/bootmode.c
+++ b/src/lib/bootmode.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
#include <bootmode.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c
index 2a057d6..d75597e 100644
--- a/src/lib/cbmem_common.c
+++ b/src/lib/cbmem_common.c
@@ -15,7 +15,6 @@
#include <console/console.h>
#include <cbmem.h>
#include <bootstate.h>
-#include <rules.h>
#include <symbols.h>
#if IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
#include <arch/acpi.h>
diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c
index 2a99188..1f1c0e4 100644
--- a/src/lib/ext_stage_cache.c
+++ b/src/lib/ext_stage_cache.c
@@ -18,7 +18,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <imd.h>
-#include <rules.h>
#include <stage_cache.h>
#include <string.h>
diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c
index b0273f4..2037ec9 100644
--- a/src/lib/imd_cbmem.c
+++ b/src/lib/imd_cbmem.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <cbmem.h>
#include <imd.h>
-#include <rules.h>
#include <string.h>
#include <stdlib.h>
#include <arch/early_variables.h>
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 3a6f2e2..54e5967 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -25,7 +25,6 @@
#include <reset.h>
#include <romstage_handoff.h>
#include <rmodule.h>
-#include <rules.h>
#include <stage_cache.h>
#include <symbols.h>
#include <timestamp.h>
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index 2f2a5d8..71dd3a9 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -22,7 +22,6 @@
#include <timer.h>
#include <timestamp.h>
#include <arch/early_variables.h>
-#include <rules.h>
#include <smp/node.h>
#define MAX_TIMESTAMPS 84
diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c
index fdd1486..416790e 100644
--- a/src/mainboard/google/chell/chromeos.c
+++ b/src/mainboard/google/chell/chromeos.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <string.h>
diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c
index 672bc97..5ee4bf4 100644
--- a/src/mainboard/google/cyan/chromeos.c
+++ b/src/mainboard/google/cyan/chromeos.c
@@ -15,7 +15,6 @@
*/
#include <arch/io.h>
-#include <rules.h>
#include <soc/gpio.h>
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c
index de83eaa..a03e5cf 100644
--- a/src/mainboard/google/eve/chromeos.c
+++ b/src/mainboard/google/eve/chromeos.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c
index 9ee6e6f..2f655f9 100644
--- a/src/mainboard/google/glados/chromeos.c
+++ b/src/mainboard/google/glados/chromeos.c
@@ -15,7 +15,6 @@
*/
#include <bootmode.h>
-#include <rules.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <string.h>
diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c
index 42763a7..6ab7c73 100644
--- a/src/mainboard/google/lars/chromeos.c
+++ b/src/mainboard/google/lars/chromeos.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <string.h>
diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c
index 646216b..0382b6c 100644
--- a/src/mainboard/google/reef/ec.c
+++ b/src/mainboard/google/reef/ec.c
@@ -17,7 +17,6 @@
#include <console/console.h>
#include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
-#include <rules.h>
#include <soc/lpc.h>
#include <variant/ec.h>
diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c
index da15795..ba773c5 100644
--- a/src/mainboard/google/storm/mmu.c
+++ b/src/mainboard/google/storm/mmu.c
@@ -11,7 +11,6 @@
*/
#include <arch/cache.h>
-#include <rules.h>
#include <soc/soc_services.h>
#include <symbols.h>
#include "mmu.h"
diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c
index fc1bcd2..bed876d 100644
--- a/src/mainboard/intel/kblrvp/chromeos.c
+++ b/src/mainboard/intel/kblrvp/chromeos.c
@@ -18,7 +18,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <rules.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <string.h>
diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c
index 42763a7..6ab7c73 100644
--- a/src/mainboard/intel/kunimitsu/chromeos.c
+++ b/src/mainboard/intel/kunimitsu/chromeos.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <string.h>
diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c
index 6d00d72..1197efd 100644
--- a/src/mainboard/intel/strago/chromeos.c
+++ b/src/mainboard/intel/strago/chromeos.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <rules.h>
#include <gpio.h>
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h
index ba4cfdd..92e99fb 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.h
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.h
@@ -23,7 +23,6 @@
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
-#include <rules.h>
#include <device/device.h>
/* Device 0:0.0 PCI configuration space (Host Bridge) */
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index b9d2cb7..9960951 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -21,7 +21,6 @@
#ifndef __ACPI__
-#include <rules.h>
#include <stdint.h>
typedef enum {
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index e737e50..35a56a2 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -62,7 +62,6 @@
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
-#include <rules.h>
/* Device 0:0.0 PCI configuration space (Host Bridge) */
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index d058f8b..48fa499 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -15,7 +15,6 @@
#ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_
#define _SOC_APOLLOLAKE_PCI_DEVS_H_
-#include <rules.h>
#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
#define _PCI_DEVFN(slot, func) PCI_DEVFN(slot, func)
diff --git a/src/soc/intel/apollolake/p2sb.c b/src/soc/intel/apollolake/p2sb.c
index 7834e38..93cdd20 100644
--- a/src/soc/intel/apollolake/p2sb.c
+++ b/src/soc/intel/apollolake/p2sb.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <rules.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pci_ids.h>
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index c88e5ae..9279545 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -21,7 +21,6 @@
#include <arch/io.h>
#include <console/console.h>
#include <cbmem.h>
-#include <rules.h>
#include <device/pci_def.h>
#include <halt.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 0e866a5..2972037 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -32,7 +32,6 @@
#include <device/pci_ids.h>
#include <ec/google/chromeec/ec.h>
#include <fsp/gop.h>
-#include <rules.h>
#include <soc/acpi.h>
#include <soc/gfx.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h
index c0b3f06..7b5b577 100644
--- a/src/soc/intel/braswell/include/soc/iosf.h
+++ b/src/soc/intel/braswell/include/soc/iosf.h
@@ -17,7 +17,6 @@
#ifndef _SOC_IOSF_H_
#define _SOC_IOSF_H_
-#include <rules.h>
#include <stdint.h>
#if ENV_RAMSTAGE
#include <device/device.h>
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index d3dfd28..44364a0 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -18,7 +18,6 @@
#ifndef _SOC_NVS_H_
#define _SOC_NVS_H_
-#include <rules.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h
index 13b511a..93065a2 100644
--- a/src/soc/intel/braswell/include/soc/smm.h
+++ b/src/soc/intel/braswell/include/soc/smm.h
@@ -17,7 +17,6 @@
#ifndef _SOC_SMM_H_
#define _SOC_SMM_H_
-#include <rules.h>
#if ENV_RAMSTAGE
#include <stdint.h>
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 018915c..6e768f2 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -16,7 +16,6 @@
#include <arch/io.h>
#include <console/console.h>
-#include <rules.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 97ca2e5..ebc3fed 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <delay.h>
#include <device/pci_ids.h>
-#include <rules.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <spi-generic.h>
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index 929b6b5..24e8b56 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -16,7 +16,6 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
-#include <rules.h>
#include <soc/msr.h>
#include <console/console.h>
#if ENV_RAMSTAGE
diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S
index b820711..7a7789b 100644
--- a/src/soc/intel/quark/romstage/car_stage_entry.S
+++ b/src/soc/intel/quark/romstage/car_stage_entry.S
@@ -18,7 +18,6 @@
* Replacement for cache_as_ram.inc when using the C environment boot block.
*/
-#include <rules.h>
#include <soc/sd.h>
.section ".text"
diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S
index 3f8f0f0..a5dab01 100644
--- a/src/soc/intel/skylake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S
@@ -18,7 +18,6 @@
#include <cpu/x86/cr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
-#include <rules.h>
#define IA32_PQR_ASSOC 0x0c8f
#define IA32_L3_MASK_1 0x0c91
diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index 0050067..06b7df5 100644
--- a/src/soc/intel/skylake/include/soc/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -16,7 +16,6 @@
#ifndef _SOC_FLASH_CONTROLLER__H_
#define _SOC_FLASH_CONTROLLER__H_
-#include <rules.h>
#include <arch/io.h>
#include <console/console.h>
#include <spi_flash.h>
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index cb3b2c6..c1a4462 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -18,7 +18,6 @@
#ifndef _SOC_NVS_H_
#define _SOC_NVS_H_
-#include <rules.h>
#include <vendorcode/google/chromeos/gnvs.h>
typedef struct {
diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h
index 701a6f5..43d0fa5 100644
--- a/src/soc/intel/skylake/include/soc/pch.h
+++ b/src/soc/intel/skylake/include/soc/pch.h
@@ -19,7 +19,6 @@
#define _SOC_PCH_H_
#include <device/device.h>
-#include <rules.h>
/* PCH (SunRisePoint LP) */
#define PCH_SPT_LP_SAMPLE 0x9d41
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 974f1d8..239a1d7 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -18,7 +18,6 @@
#define _SOC_PCI_DEVS_H_
#include <device/pci_def.h>
-#include <rules.h>
#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/skylake/include/soc/xhci.h b/src/soc/intel/skylake/include/soc/xhci.h
index c520223..2db7579 100644
--- a/src/soc/intel/skylake/include/soc/xhci.h
+++ b/src/soc/intel/skylake/include/soc/xhci.h
@@ -17,7 +17,6 @@
#ifndef _SOC_XHCI_H_
#define _SOC_XHCI_H_
-#include <rules.h>
/* XHCI PCI Registers */
#define XHCI_PWR_CTL_STS 0x74
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 73dc117..8a9357a 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <halt.h>
-#include <rules.h>
#include <stdlib.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S
index c6401fa..7094129 100644
--- a/src/soc/intel/skylake/romstage/car_stage.S
+++ b/src/soc/intel/skylake/romstage/car_stage.S
@@ -14,7 +14,6 @@
*
*/
-#include <rules.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
diff --git a/src/soc/marvell/mvmap2315/uart.c b/src/soc/marvell/mvmap2315/uart.c
index 51c74fc..ab40a08 100644
--- a/src/soc/marvell/mvmap2315/uart.c
+++ b/src/soc/marvell/mvmap2315/uart.c
@@ -19,7 +19,6 @@
#include <assert.h>
#include <console/uart.h>
-#include <rules.h>
#include <stdint.h>
#include <soc/uart.h>
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld
index c1c581b..13c2966 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld
@@ -14,7 +14,6 @@
*/
#include <memlayout.h>
-#include <rules.h>
#include <arch/header.ld>
diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c
index 5bb7040..11b86ea 100644
--- a/src/vboot/bootmode.c
+++ b/src/vboot/bootmode.c
@@ -16,7 +16,6 @@
#include <assert.h>
#include <bootmode.h>
#include <bootstate.h>
-#include <rules.h>
#include <string.h>
#include <vb2_api.h>
#include <vboot/misc.h>
diff --git a/src/vboot/vboot_common.c b/src/vboot/vboot_common.c
index 515b368..62800a4 100644
--- a/src/vboot/vboot_common.c
+++ b/src/vboot/vboot_common.c
@@ -20,7 +20,6 @@
#include <console/console.h>
#include <fmap.h>
#include <reset.h>
-#include <rules.h>
#include <stddef.h>
#include <string.h>
#include <vboot/vboot_common.h>
diff --git a/src/vboot/vboot_loader.c b/src/vboot/vboot_loader.c
index 207aada..2dd4799 100644
--- a/src/vboot/vboot_loader.c
+++ b/src/vboot/vboot_loader.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <rmodule.h>
-#include <rules.h>
#include <string.h>
#include <vboot/misc.h>
#include <vboot/symbols.h>
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index fd845bf..25c60c9 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <bootmode.h>
#include <device/device.h>
-#include <rules.h>
#include <vboot/misc.h>
#include <vboot/vboot_common.h>
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