[coreboot-gerrit] Patch set updated for coreboot: mb/intel/kblrvp: Add Variant board support for KBLRVP
Barnali Sarkar (barnali.sarkar@intel.com)
gerrit at coreboot.org
Wed Nov 30 11:45:32 CET 2016
Barnali Sarkar (barnali.sarkar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17630
-gerrit
commit 4c499b37e6466cd11bb5da6b167c64c479cf279b
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date: Mon Nov 28 14:53:12 2016 +0530
mb/intel/kblrvp: Add Variant board support for KBLRVP
Add support of Variant board model for existing intel/kblrvp,
since there might be more RVP board supports under
intel/kblrvp. Existing is for KBL RVP3 board.
BUG=none
BRANCH=none
TEST=Built and boot Kaby Lake RVP3
Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
src/Kconfig | 2 +-
src/mainboard/intel/kblrvp/Kconfig | 8 +
src/mainboard/intel/kblrvp/Makefile.inc | 3 +
src/mainboard/intel/kblrvp/acpi/ec.asl | 2 +-
src/mainboard/intel/kblrvp/acpi/mainboard.asl | 2 +-
src/mainboard/intel/kblrvp/bootblock.c | 2 +-
src/mainboard/intel/kblrvp/devicetree.cb | 262 ---------------------
src/mainboard/intel/kblrvp/gpio.h | 218 -----------------
src/mainboard/intel/kblrvp/mainboard.c | 2 +-
src/mainboard/intel/kblrvp/ramstage.c | 2 +-
src/mainboard/intel/kblrvp/smihandler.c | 2 +-
src/mainboard/intel/kblrvp/spd/spd.h | 3 +-
.../intel/kblrvp/variants/rvp3/devicetree.cb | 262 +++++++++++++++++++++
.../kblrvp/variants/rvp3/include/variant/gpio.h | 218 +++++++++++++++++
14 files changed, 499 insertions(+), 489 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 77d13d1..5cd0254 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -326,7 +326,7 @@ config GENERIC_SPD_BIN
config DIMM_MAX
int
- default 2
+ default 4
depends on GENERIC_SPD_BIN
help
Total number of memory DIMM slots available on motherboard.
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index e53c446..10752e7 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -48,6 +48,10 @@ config MAINBOARD_DIR
string
default "intel/kblrvp"
+config VARIANT_DIR
+ string
+ default "rvp3"
+
config MAINBOARD_PART_NUMBER
string
default "Kblrvp"
@@ -68,4 +72,8 @@ config GBB_HWID
string
depends on CHROMEOS
default "KBLRVP TEST 8819"
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
endif
diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc
index 68c87c9..7ddfb9f 100644
--- a/src/mainboard/intel/kblrvp/Makefile.inc
+++ b/src/mainboard/intel/kblrvp/Makefile.inc
@@ -32,3 +32,6 @@ ramstage-y += mainboard.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl
index 7d7ff2f..01fa75c 100644
--- a/src/mainboard/intel/kblrvp/acpi/ec.asl
+++ b/src/mainboard/intel/kblrvp/acpi/ec.asl
@@ -15,7 +15,7 @@
/* mainboard configuration */
#include "../ec.h"
-#include "../gpio.h"
+#include <variant/gpio.h>
/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE
diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
index 5d2b307..4764372 100644
--- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl
+++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#include "../gpio.h"
+#include <variant/gpio.h>
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
Scope (\_SB)
diff --git a/src/mainboard/intel/kblrvp/bootblock.c b/src/mainboard/intel/kblrvp/bootblock.c
index 627b4e8..dde7e86 100644
--- a/src/mainboard/intel/kblrvp/bootblock.c
+++ b/src/mainboard/intel/kblrvp/bootblock.c
@@ -15,7 +15,7 @@
#include <bootblock_common.h>
#include <soc/gpio.h>
-#include "gpio.h"
+#include <variant/gpio.h>
static void early_config_gpio(void)
{
diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb
deleted file mode 100644
index c2dde4f..0000000
--- a/src/mainboard/intel/kblrvp/devicetree.cb
+++ /dev/null
@@ -1,262 +0,0 @@
-chip soc/intel/skylake
-
- # Enable deep Sx states
- register "deep_s5_enable" = "0"
- register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
-
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_C"
- register "gpe0_dw1" = "GPP_D"
- register "gpe0_dw2" = "GPP_E"
-
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
-
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
- # Enable DPTF
- register "dptf_enable" = "1"
-
- # FSP Configuration
- register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "1"
- register "ScsEmmcHs400Enabled" = "1"
- register "ScsSdCardEnabled" = "2"
- register "InternalGfx" = "1"
- register "SkipExtGfxScan" = "1"
- register "Device4Enable" = "1"
- register "HeciEnabled" = "0"
- register "SaGv" = "3"
- register "PmTimerDisabled" = "1"
-
- register "pirqa_routing" = "PCH_IRQ11"
- register "pirqb_routing" = "PCH_IRQ10"
- register "pirqc_routing" = "PCH_IRQ11"
- register "pirqd_routing" = "PCH_IRQ11"
- register "pirqe_routing" = "PCH_IRQ11"
- register "pirqf_routing" = "PCH_IRQ11"
- register "pirqg_routing" = "PCH_IRQ11"
- register "pirqh_routing" = "PCH_IRQ11"
-
- # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
- # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
- register "PmConfigSlpS3MinAssert" = "0x02"
-
- # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
- register "PmConfigSlpS4MinAssert" = "0x04"
-
- # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
- register "PmConfigSlpSusMinAssert" = "0x03"
-
- # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
- register "PmConfigSlpAMinAssert" = "0x03"
-
- # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
- register "SerialIrqConfigSirqEnable" = "0x01"
-
- # VR Settings Configuration for 5 Domains
- #+----------------+-------+-------+-------------+-------------+-------+
- #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
- #+----------------+-------+-------+-------------+-------------+-------+
- #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
- #| Psi2Threshold | 5A | 5A | 5A | 5A | 5A |
- #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
- #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
- #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
- #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
- #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
- #| IccMax | 7A | 34A | 34A | 35A | 35A |
- #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
- #+----------------+-------+-------+-------------+-------------+-------+
- register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x1C, \
- .voltage_limit = 0x5F0 \
- }"
-
- register "domain_vr_config[VR_IA_CORE]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x88, \
- .voltage_limit = 0x5F0 \
- }"
- register "domain_vr_config[VR_RING]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x88, \
- .voltage_limit = 0x5F0, \
- }"
-
- register "domain_vr_config[VR_GT_UNSLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x8C ,\
- .voltage_limit = 0x5F0 \
- }"
-
- register "domain_vr_config[VR_GT_SLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = 0x50, \
- .psi2threshold = 0x14, \
- .psi3threshold = 0x4, \
- .psi3enable = 1, \
- .psi4enable = 1, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0x8C, \
- .voltage_limit = 0x5F0 \
- }"
-
- register "FspSkipMpInit" = "1"
-
- # Enable Root ports.
- # PCIE Port 1 x4 -> SLOT1
- register "PcieRpEnable[0]" = "1"
- register "PcieRpClkReqSupport[0]" = "1"
- register "PcieRpClkReqNumber[0]" = "2"
-
- # PCIE Port 5 x1 -> SLOT2/LAN
- register "PcieRpEnable[4]" = "1"
- register "PcieRpClkReqSupport[4]" = "1"
- register "PcieRpClkReqNumber[4]" = "3"
-
- # PCIE Port 6 x1 -> SLOT3
- register "PcieRpEnable[5]" = "1"
- register "PcieRpClkReqSupport[5]" = "1"
- register "PcieRpClkReqNumber[5]" = "1"
-
- # PCIE Port 7 Disabled
- # PCIE Port 8 Disabled
- # PCIE Port 9 x1 -> WLAN
- register "PcieRpEnable[8]" = "1"
- register "PcieRpClkReqSupport[8]" = "1"
- register "PcieRpClkReqNumber[8]" = "5"
-
- # PCIE Port 10 x1 -> WiGig
- register "PcieRpEnable[9]" = "1"
- register "PcieRpClkReqSupport[9]" = "1"
- register "PcieRpClkReqNumber[9]" = "4"
-
- # USB 2.0 Enable all ports
- register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
- register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
- register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port
- register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
- register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port
- register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
-
- # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
- register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
- register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
-
- register "SsicPortEnable" = "1" # Enable SSIC for WWAN
-
- # Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
- [PchSerialIoIndexI2C4] = PchSerialIoPci, \
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart0] = PchSerialIoPci, \
- [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
- }"
-
- # Send an extra VR mailbox command for the PS4 exit issue
- register "SendVrMbxCmd" = "2"
-
- # Enable/Disable VMX feature
- register "VmxEnable" = "0"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 14.0 on end # USB xHCI
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # Thermal Subsystem
- device pci 15.0 on end # I2C #0
- device pci 15.1 on end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 17.0 off end # SATA
- device pci 19.0 on end # UART #2
- device pci 19.1 off end # I2C #5
- device pci 19.2 on end
- device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
- device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
- device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on end # PCI Express Port 9 x1 WLAN
- device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG
- device pci 1e.0 on end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1e.4 on end # eMMC
- device pci 1e.5 off end # SDIO
- device pci 1e.6 on end # SDCard
- device pci 1f.0 on
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- end # LPC Interface
- device pci 1f.1 on end # P2SB
- device pci 1f.2 on end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
- end
-end
diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h
deleted file mode 100644
index c6f4123..0000000
--- a/src/mainboard/intel/kblrvp/gpio.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2016 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- */
-
-#ifndef MAINBOARD_GPIO_H
-#define MAINBOARD_GPIO_H
-
-#include <soc/gpe.h>
-#include <soc/gpio.h>
-
-/* TCA6424A I/O Expander */
-#define IO_EXPANDER_BUS 4
-#define IO_EXPANDER_0_ADDR 0x22
-#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */
-#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */
-#define IO_EXPANDER_P1CONF 0x0D
-#define IO_EXPANDER_P1DOUT 0x05
-#define IO_EXPANDER_P2CONF 0x0E
-#define IO_EXPANDER_P2DOUT 0x06
-#define IO_EXPANDER_1_ADDR 0x23
-
-/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
-#define GPE_EC_WAKE GPE0_LAN_WAK
-
-/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
-#define EC_SCI_GPI GPE0_DW2_16
-#define EC_SMI_GPI GPP_E15
-
-#ifndef __ACPI__
-/* Pad configuration in ramstage. */
-static const struct pad_config gpio_table[] = {
-/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1),
-/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1),
-/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1),
-/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1),
-/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
-/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PM_SLP_S0ix_N */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
-/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
-/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
-/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
-/* EC_HID_INT */ PAD_CFG_NC(GPP_A11),
-/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12),
-/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),
-/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
-/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
-/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
-/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
-/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
-/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
-/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
-/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
-/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
-/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0),
-/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1),
-/* GP_VRALERTB */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
-/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
-/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP),
-/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5),
-/* CLK_REQ_SLOT1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
-/* CLK_REQ_SLOT2 */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
-/* CLK_REQ_SLOT3 */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
-/* CLK_REQ_SLOT4 */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-/* CLK_REQ_SLOT5 */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
-/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
-/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
-/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_B14, 1, DEEP),
-/* GSPI0_CS# */ /* GPP_B15 */
-/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
-/* TBT_CIO */ PAD_CFG_NC(GPP_B17),
-/* SLOT1_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES),
-/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
-/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
-/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
-/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
-/* GNSS_RESET */ PAD_CFG_GPO(GPP_B23, 1, DEEP),
-/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
-/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
-/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP),
-/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
-/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST),
-/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
-/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
-/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
-/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
-/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
-/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
-/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
-/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
-/* UART1_RTS */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
-/* UART1_CTS */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
-/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
-/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
-/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-/* UART2_RTS */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
-/* UART2_CTS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
-/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
-/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
-/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
-/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
-/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
-/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
-/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
-/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
-/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
-/* HOME_BTN */ PAD_CFG_GPI(GPP_D9, NONE, DEEP),
-/* SCREEN_LOCK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),
-/* VOL_UP_PCH */ PAD_CFG_GPI(GPP_D11, NONE, DEEP),
-/* VOL_DOWN_PCH */ PAD_CFG_GPI(GPP_D12, NONE, DEEP),
-/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
-/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
-/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
-/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
-/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
-/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
-/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
-/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
-/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
-/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
-/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
-/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
-/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
-/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
-/* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP),
-/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
-/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
-/* SATA_DEVSLP2 */ /* GPP_E6 */
-/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
-/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
-/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
-/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
-/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
-/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST),
-/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
-/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
-/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
-/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
-/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
-/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
-/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
-/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
-/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
-/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
-/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
-/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
-/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
-/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
-/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
-/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
-/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
-/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
-/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
-/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2),
-/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2),
-/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
-/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
-/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
-/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
-/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
-/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
-/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
-/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
-/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
-/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
-/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-/* UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
-/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
-/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
-/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
-/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
-/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
-/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
-/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
-/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
-/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
-/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
-/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
-/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
-/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
-/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
-/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
-/* GPD7 */ PAD_CFG_NC(GPD7),
-/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
-/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
-/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
-};
-
-/* Early pad configuration in romstage. */
-static const struct pad_config early_gpio_table[] = {
-/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
-/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
-};
-
-#endif
-
-#endif
diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c
index cd6c3f9..652af73 100644
--- a/src/mainboard/intel/kblrvp/mainboard.c
+++ b/src/mainboard/intel/kblrvp/mainboard.c
@@ -24,7 +24,7 @@
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
-#include "gpio.h"
+#include <variant/gpio.h>
static void mainboard_init(device_t dev)
{
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index bcd72bc..3a48396 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -17,7 +17,7 @@
#include <console/console.h>
#include <device/i2c.h>
#include <soc/ramstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c
index 81aaf23..9ecc43a 100644
--- a/src/mainboard/intel/kblrvp/smihandler.c
+++ b/src/mainboard/intel/kblrvp/smihandler.c
@@ -25,7 +25,7 @@
#include <soc/pm.h>
#include <soc/smm.h>
#include "ec.h"
-#include "gpio.h"
+#include <variant/gpio.h>
int mainboard_io_trap_handler(int smif)
{
diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h
index 3ef2dd8..c24baa0 100644
--- a/src/mainboard/intel/kblrvp/spd/spd.h
+++ b/src/mainboard/intel/kblrvp/spd/spd.h
@@ -18,8 +18,7 @@
#define MAINBOARD_SPD_H
#include <gpio.h>
-#include "../gpio.h"
-
+#include <variant/gpio.h>
#define RCOMP_TARGET_PARAMS 0x5
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
new file mode 100644
index 0000000..c2dde4f
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
@@ -0,0 +1,262 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s5_enable" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # FSP Configuration
+ register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "2"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "SaGv" = "3"
+ register "PmTimerDisabled" = "1"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+ register "PmConfigSlpS3MinAssert" = "0x02"
+
+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+ register "PmConfigSlpS4MinAssert" = "0x04"
+
+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+ register "PmConfigSlpSusMinAssert" = "0x03"
+
+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+ register "PmConfigSlpAMinAssert" = "0x03"
+
+ # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
+ register "SerialIrqConfigSirqEnable" = "0x01"
+
+ # VR Settings Configuration for 5 Domains
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 5A | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x1C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x88, \
+ .voltage_limit = 0x5F0 \
+ }"
+ register "domain_vr_config[VR_RING]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x88, \
+ .voltage_limit = 0x5F0, \
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x8C ,\
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x8C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "FspSkipMpInit" = "1"
+
+ # Enable Root ports.
+ # PCIE Port 1 x4 -> SLOT1
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "2"
+
+ # PCIE Port 5 x1 -> SLOT2/LAN
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "3"
+
+ # PCIE Port 6 x1 -> SLOT3
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpClkReqSupport[5]" = "1"
+ register "PcieRpClkReqNumber[5]" = "1"
+
+ # PCIE Port 7 Disabled
+ # PCIE Port 8 Disabled
+ # PCIE Port 9 x1 -> WLAN
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "5"
+
+ # PCIE Port 10 x1 -> WiGig
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpClkReqSupport[9]" = "1"
+ register "PcieRpClkReqNumber[9]" = "4"
+
+ # USB 2.0 Enable all ports
+ register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
+ register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
+ register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port
+ register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
+ register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port
+ register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+
+ # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
+ register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
+ register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
+
+ register "SsicPortEnable" = "1" # Enable SSIC for WWAN
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ }"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Enable/Disable VMX feature
+ register "VmxEnable" = "0"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on end
+ device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
+ device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
+ device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9 x1 WLAN
+ device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 on end # SDCard
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
new file mode 100644
index 0000000..c6f4123
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
@@ -0,0 +1,218 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* TCA6424A I/O Expander */
+#define IO_EXPANDER_BUS 4
+#define IO_EXPANDER_0_ADDR 0x22
+#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */
+#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */
+#define IO_EXPANDER_P1CONF 0x0D
+#define IO_EXPANDER_P1DOUT 0x05
+#define IO_EXPANDER_P2CONF 0x0E
+#define IO_EXPANDER_P2DOUT 0x06
+#define IO_EXPANDER_1_ADDR 0x23
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
+#define EC_SCI_GPI GPE0_DW2_16
+#define EC_SMI_GPI GPP_E15
+
+#ifndef __ACPI__
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1),
+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1),
+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1),
+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1),
+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* PM_SLP_S0ix_N */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
+/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
+/* EC_HID_INT */ PAD_CFG_NC(GPP_A11),
+/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12),
+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),
+/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
+/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
+/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
+/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0),
+/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1),
+/* GP_VRALERTB */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
+/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP),
+/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5),
+/* CLK_REQ_SLOT1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+/* CLK_REQ_SLOT2 */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+/* CLK_REQ_SLOT3 */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+/* CLK_REQ_SLOT4 */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+/* CLK_REQ_SLOT5 */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_B14, 1, DEEP),
+/* GSPI0_CS# */ /* GPP_B15 */
+/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
+/* TBT_CIO */ PAD_CFG_NC(GPP_B17),
+/* SLOT1_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES),
+/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
+/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
+/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
+/* GNSS_RESET */ PAD_CFG_GPO(GPP_B23, 1, DEEP),
+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP),
+/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST),
+/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+/* UART1_RTS */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+/* UART1_CTS */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+/* UART2_RTS */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+/* UART2_CTS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
+/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
+/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+/* HOME_BTN */ PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+/* SCREEN_LOCK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),
+/* VOL_UP_PCH */ PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+/* VOL_DOWN_PCH */ PAD_CFG_GPI(GPP_D12, NONE, DEEP),
+/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
+/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
+/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
+/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+/* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP),
+/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+/* SATA_DEVSLP2 */ /* GPP_E6 */
+/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
+/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST),
+/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
+/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1),
+/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
+/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
+/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
+/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
+/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
+/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
+/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
+/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
+/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2),
+/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2),
+/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
+/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+/* GPD7 */ PAD_CFG_NC(GPD7),
+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+};
+
+#endif
+
+#endif
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