[coreboot-gerrit] New patch to review for coreboot: lib/edid.c: Remove trailing space from detailed mode output

[Paul Menzel (paulepanter@users.sourceforge.net)]

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17644

-gerrit

commit cc9395d6cc9985e8183a3ae3cb3bdb4f6876b267
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Tue Nov 29 21:02:04 2016 +0100

    lib/edid.c: Remove trailing space from detailed mode output
    
    When the bit for interlaced mode is not set, a trailing space is added
    to the end.
    
    As the space is already accounted for in `" interlaced"`, remove that
    space.
    
    TEST=Boot on Lenovo X60t, and verify the trailing space in the detailed
         mode is gone.
    
    Change-Id: I4114c9e61a040fa005c806404ec51c12e2f02f4d
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/lib/edid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib/edid.c b/src/lib/edid.c
index 23b6503..edc2af1 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -585,7 +585,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension,
 	       "Detailed mode (IN HEX): Clock %d KHz, %x mm x %x mm\n"
 	       "               %04x %04x %04x %04x hborder %x\n"
 	       "               %04x %04x %04x %04x vborder %x\n"
-	       "               %chsync %cvsync%s%s %s\n", out->mode.pixel_clock,
+	       "               %chsync %cvsync%s%s%s\n", out->mode.pixel_clock,
 	       extra_info.x_mm, extra_info.y_mm, out->mode.ha,
 	       out->mode.ha + out->mode.hso,
 	       out->mode.ha + out->mode.hso + out->mode.hspw,