[coreboot-gerrit] Patch set updated for coreboot: mb/intel/kblrvp: Use common lib spd_bin to get spd
Naresh Solanki (naresh.solanki@intel.com)
gerrit at coreboot.org
Tue Nov 29 21:14:57 CET 2016
Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17435
-gerrit
commit f79bb6e9606448951bc13c935bb62d1d35451d04
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date: Tue Nov 15 19:35:33 2016 +0530
mb/intel/kblrvp: Use common lib spd_bin to get spd
Use common lib spd_bin to get spd.
Change-Id: If94413fc36a98f7694f560955bbb80abefe32166
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
src/mainboard/intel/kblrvp/Kconfig | 1 +
src/mainboard/intel/kblrvp/romstage.c | 21 +++++--
src/mainboard/intel/kblrvp/spd/Makefile.inc | 14 -----
src/mainboard/intel/kblrvp/spd/spd.c | 94 -----------------------------
src/mainboard/intel/kblrvp/spd/spd.h | 18 +-----
src/mainboard/intel/kblrvp/spd/spd_util.c | 34 -----------
6 files changed, 19 insertions(+), 163 deletions(-)
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index 446266d..e53c446 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_INTEL_SKYLAKE
select MAINBOARD_USES_FSP2_0
select MAINBOARD_HAS_CHROMEOS
+ select GENERIC_SPD_BIN
config CHROMEOS
select LID_SWITCH
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
index d4fd113..bc39a80 100644
--- a/src/mainboard/intel/kblrvp/romstage.c
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -23,20 +23,33 @@
#include <soc/gpio.h>
#include "spd/spd.h"
#include <string.h>
+#include <spd_bin.h>
+#include "board_id.h"
+
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg;
mem_cfg = &mupd->FspmConfig;
+ struct region_device spd_rdev;
+ u8 spd_index = (get_board_id() >> 5) & 0x7;
+
+ printk(BIOS_INFO, "SPD index %d\n", spd_index);
mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+ /* RVP3 SPD */
mem_cfg->DqPinsInterleaved = 0;
- mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
- if (mainboard_has_dual_channel_mem())
- mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
- mem_cfg->MemorySpdDataLen = SPD_LEN;
+
+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) {
+ die("spd.bin not found\n");
+ }
+
+ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
+ /* Memory leak is ok since we have memory mapped boot media */
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
}
diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc
index 83f4831..0c864fe 100644
--- a/src/mainboard/intel/kblrvp/spd/Makefile.inc
+++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc
@@ -26,17 +26,3 @@ SPD_SOURCES += empty # 4b100
SPD_SOURCES += empty # 5b101
SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 6b110 Dual Channel 8GB
SPD_SOURCES += empty # 7b111
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
- for f in $+; \
- do for c in $$(cat $$f | grep -v ^#); \
- do printf $$(printf '\%o' 0x$$c); \
- done; \
- done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
diff --git a/src/mainboard/intel/kblrvp/spd/spd.c b/src/mainboard/intel/kblrvp/spd/spd.c
deleted file mode 100644
index 1abee81..0000000
--- a/src/mainboard/intel/kblrvp/spd/spd.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/byteorder.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <string.h>
-
-#include "spd.h"
-
-static void mainboard_print_spd_info(uint8_t spd[])
-{
- const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
- const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
- const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
- const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
- const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
- const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
- char spd_name[SPD_PART_LEN+1] = { 0 };
-
- int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
- int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
- int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
- int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
- int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
- int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
- int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
-
- /* Module type */
- printk(BIOS_INFO, "SPD: module type is ");
- switch (spd[SPD_DRAM_TYPE]) {
- case SPD_DRAM_DDR3:
- printk(BIOS_INFO, "DDR3\n");
- break;
- case SPD_DRAM_LPDDR3:
- case SPD_DRAM_LPDDR3_INTEL:
- printk(BIOS_INFO, "LPDDR3\n");
- break;
- default:
- printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
- break;
- }
-
- /* Module Part Number */
- memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
- spd_name[SPD_PART_LEN] = 0;
- printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
-
- printk(BIOS_INFO,
- "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
- banks, ranks, rows, cols, capmb);
- printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
- devw, busw);
-
- if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
- /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
- printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
- capmb / 8 * busw / devw * ranks);
- }
-}
-
-/* Copy SPD data for on-board memory */
-void mainboard_fill_spd_data(struct pei_data *pei_data)
-{
- uintptr_t spd_data;
- spd_data = mainboard_get_spd_data();
-
- memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN);
-
- if (mainboard_has_dual_channel_mem())
- memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN);
-
- /* Make sure a valid SPD was found */
- if (pei_data->spd_data[0][0][0] == 0)
- die("Invalid SPD data.");
-
- mainboard_print_spd_info(pei_data->spd_data[0][0]);
-}
diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h
index a9f8645..3ef2dd8 100644
--- a/src/mainboard/intel/kblrvp/spd/spd.h
+++ b/src/mainboard/intel/kblrvp/spd/spd.h
@@ -15,25 +15,11 @@
*/
#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
#include <gpio.h>
#include "../gpio.h"
-#define MAINBOARD_SPD_H
-
-#define SPD_LEN 256
-
-#define SPD_DRAM_TYPE 2
-#define SPD_DRAM_DDR3 0x0B
-#define SPD_DRAM_LPDDR3 0x0F
-#define SPD_DRAM_LPDDR3_INTEL 0xF1
-#define SPD_DENSITY_BANKS 4
-#define SPD_ADDRESSING 5
-#define SPD_ORGANIZATION 7
-#define SPD_BUS_DEV_WIDTH 8
-#define SPD_PART_OFF 128
-#define SPD_PART_LEN 18
-#define SPD_MANU_OFF 148
#define RCOMP_TARGET_PARAMS 0x5
@@ -41,6 +27,4 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr);
void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
-uintptr_t mainboard_get_spd_data(void);
-int mainboard_has_dual_channel_mem(void);
#endif
diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c
index 9ffc8ee..181af9f 100644
--- a/src/mainboard/intel/kblrvp/spd/spd_util.c
+++ b/src/mainboard/intel/kblrvp/spd/spd_util.c
@@ -58,37 +58,3 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
}
-
-uintptr_t mainboard_get_spd_data(void)
-{
- char *spd_file;
- int spd_index, spd_span;
- size_t spd_file_len;
-
- spd_index = (get_board_id() >> 5) & 0xF;
- printk(BIOS_INFO, "SPD index %d\n", spd_index);
-
- /* Load SPD data from CBFS */
- spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
- &spd_file_len);
- if (!spd_file)
- die("SPD data not found.");
-
- /* make sure we have at least one SPD in the file. */
- if (spd_file_len < SPD_LEN)
- die("Missing SPD data.");
-
- /* Make sure we did not overrun the buffer */
- if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
- printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
- spd_index = 0;
- }
-
- spd_span = spd_index * SPD_LEN;
- return (uintptr_t)(spd_file + spd_span);
-}
-
-int mainboard_has_dual_channel_mem(void)
-{
- return 1;
-}
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