[coreboot-gerrit] Patch set updated for coreboot: mainboard/intel/kblrvp: Revert back USB OC pin programming

[Barnali Sarkar (barnali.sarkar@intel.com)]

Barnali Sarkar (barnali.sarkar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17635

-gerrit

commit 8cd0e651f6404b98ceeb786628ae4b4ad8c87fbc
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Tue Nov 29 12:05:28 2016 +0530

    mainboard/intel/kblrvp: Revert back USB OC pin programming
    
    With commit 2c3054c1(soc/intel/skylake: Add USB Port Over
    Current (OC) Pin programming) USB OC pin programming is already
    initiated from devicetree.cb, hence remove it from ramstage.c.
    
    BUG=none
    BRANCH=none
    TEST=Built and booted KBLRVP from USB device
    
    Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
 src/mainboard/intel/kblrvp/ramstage.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index d33c967..bcd72bc 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -21,21 +21,10 @@
 
 void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {
-	size_t i;
 	/* Configure pads prior to SiliconInit() in case there's any
 	 * dependencies during hardware initialization. */
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 	params->CdClock = 3;
-
-	/* Set proper OC for various USB ports*/
-	u8 usb2_oc[] = {0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8};
-	u8 usb3_oc[] = {0x0, 0x8, 0x8, 0x1, 0x8, 0x8};
-
-	for (i = 0; i < ARRAY_SIZE(usb2_oc); i++)
-		params->Usb2OverCurrentPin[i] = usb2_oc[i];
-
-	for (i = 0; i < ARRAY_SIZE(usb3_oc); i++)
-		params->Usb3OverCurrentPin[i] = usb3_oc[i];
 }
 
 static void ioexpander_init(void *unused)