[coreboot-gerrit] Patch set updated for coreboot: soc/skylake: Move IO decode range out from pch_lpc_init
Boon Tiong Teo (boon.tiong.teo@intel.com)
gerrit at coreboot.org
Tue Nov 29 09:48:54 CET 2016
Boon Tiong Teo (boon.tiong.teo at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17337
-gerrit
commit a3b1f120003ffeb9350e72ab49bffd17fbf7c81a
Author: Teo Boon Tiong <boon.tiong.teo at intel.com>
Date: Thu Nov 10 01:21:23 2016 +0800
soc/skylake: Move IO decode range out from pch_lpc_init
1. Move existing IO decode range from pch_lpc_init to early
stage before SIO init.
2. At the same time, enable SIO decode range (0x2e/0x2f)
for platform which use super IO.
Change-Id: I72df16d0a784686d8cadfbee09b5aef60576ac43
Signed-off-by: Teo Boon Tiong <boon.tiong.teo at intel.com>
---
src/soc/intel/skylake/bootblock/bootblock.c | 1 +
src/soc/intel/skylake/bootblock/pch.c | 27 ++++++++++++++++-----------
src/soc/intel/skylake/include/soc/bootblock.h | 1 +
3 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index ea41b4b..93a031f 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -27,6 +27,7 @@ void bootblock_soc_early_init(void)
bootblock_systemagent_early_init();
bootblock_pch_early_init();
bootblock_cpu_init();
+ pch_early_iorange_init();
if (IS_ENABLED(CONFIG_UART_DEBUG))
pch_uart_init();
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 371dd63..6279cf2 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -95,17 +95,6 @@ static void pch_enable_lpc(void)
/* Lookup device tree in romstage */
const struct device *dev;
const config_t *config;
- u16 lpc_en;
-
- /* IO Decode Range */
- lpc_en = COMA_RANGE | (COMB_RANGE << 4);
- pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en);
- pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
-
- /* IO Decode Enable */
- lpc_en = COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
- pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
- pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
if (!dev || !dev->chip_info)
@@ -272,6 +261,22 @@ static void enable_heci(void)
pci_write_config8(dev, PCI_COMMAND, pcireg);
}
+void pch_early_iorange_init(void)
+{
+ /* Lookup device tree in romstage */
+ u16 lpc_en;
+
+ /* IO Decode Range */
+ lpc_en = COMA_RANGE | (COMB_RANGE << 4);
+ pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en);
+ pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
+
+ /* IO Decode Enable */
+ lpc_en = CNF1_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
+ pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
+ pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
+}
+
void pch_early_init(void)
{
/*
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index 4895912..df81d3f 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -32,6 +32,7 @@ void pch_uart_init(void);
void enable_smbus(void);
void i2c_early_init(void);
void pch_early_init(void);
+void pch_early_iorange_init(void);
void report_platform_info(void);
void report_memory_config(void);
void set_max_freq(void);
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