[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Remove pad configuration size hardcoding

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17571

-gerrit

commit 08fcc5c218ab1c7971d7d24514486fa3a117cbd3
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Wed Nov 23 00:54:47 2016 +0530

    soc/intel/skylake: Remove pad configuration size hardcoding
    
    Existing GPIO driver inside coreboot use some hardcoded magic number
    to calculate gpio pad offset. Avoid this kind of hardcoding..
    
    Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/skylake/gpio.c                  | 3 ++-
 src/soc/intel/skylake/include/soc/gpio_defs.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 5b9babf..6334b3e 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -226,7 +226,8 @@ static void *gpio_dw_regs(gpio_t pad)
 	pad_relative = pad - comm->min;
 
 	/* DW0 and DW1 regs are 4 bytes each. */
-	return &regs[PAD_CFG_DW_OFFSET + pad_relative * 8];
+	return &regs[PAD_CFG_DW_OFFSET + pad_relative *
+			GPIO_DWx_SIZE(GPIO_DWx_COUNT)];
 }
 
 static void *gpio_hostsw_reg(gpio_t pad, size_t *bit)
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 112db63..b583522 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -33,6 +33,8 @@
 #define GPIO_NUM_GROUPS		8
 #define GPIO_MAX_NUM_PER_GROUP	24
 
+#define GPIO_DWx_COUNT		2 /* DW0 and DW1 */
+#define GPIO_DWx_SIZE(x)	(4 * (x))
 /*
  * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
  */